hbrisc2 - Microelectronics

Hbrisc2 Circuit Validation Strategy: Test Means1st test platform: VHDL simulator Allows RTL-level, gate-level (pre & post layout simulations) Suited for small test patterns (simulation is slow especially during gate-level) Easy debugging (full visibility of all internal nodes) 2nd test platform: Atmel tester (Sentry 15) Use of final physical implementation Number of test vectors is limited (Atmel quota) Atmel tester frequency limited to 20 MHz.TN0342-Iss10.pptAll right reserved: Disclosure to third parties of this document or any part thereof, or the use of any information contained therein for purposes other than provided for by this document, is not permitted exceptwith prior and express written permission of S.A.B.C.A.06/12/200425