hbrisc2 - Microelectronics

Brisc Architecture Overview: ASIC Technology ATMEL MH1RT Rad-Tolerant Latch-up immune (> 80 Mev/g/cm2) SEU hardened registers Gate-array 0.35 µm 5V I/O pads 3.3 V Core HBRISC2 Matrix: MH1_156E Package: MQFP-256 4 on-chip dual-port RAM Bank register SPI interface buffersTN0342-Iss10.pptAll right reserved: Disclosure to third parties of this document or any part thereof, or the use of any information contained therein for purposes other than provided for by this document, is not permitted exceptwith prior and express written permission of S.A.B.C.A.06/12/200417