hbrisc2 - Microelectronics

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Description of the Production and validation tools A certain number of tools have been developed around Brisc processorsin order to allow efficient production of good quality code. The main tools are the following: The synthesiser that takes a Simulink diagram and generates assembly code. The Assembler that produces binary code. The Seracq-Win32 that supports tests on target hardware. It performsuploading of a program, running of command scripts, and acquisition andvisualisation of parameters transmitted through the HSSL. The total_nw program that allows unit tests of the macros to be executed alltogether in a single run. A set of scripts that allows unit tests of the Simulink blocks to be performedautomatically.TN0342-Iss10.pptAll right reserved: Disclosure to third parties of this document or any part thereof, or the use of any information contained therein for purposes other than provided for by this document, is not permitted exceptwith prior and express written permission of S.A.B.C.A.06/12/200432
Production chain of HBRISC2 application SWSIMULINK library(lib_imcm.mdl)Macro definition(macros.lst)Macro library(bh files)TargethardwareSIMULINK modelSimplified(mdl file)SynthesisedSIMULINK model(mdl file)SYNTHESISERCode source(b2c file)CompilationHbrass2.exeBinary code(bin file)Softwarevalidationtesting(Seracq-Win32)Variabledefinition file(m files)HBrisc2 parameterinitialisation(initialisations.bc)TN0342-Iss10.pptAll right reserved: Disclosure to third parties of this document or any part thereof, or the use of any information contained therein for purposes other than provided for by this document, is not permitted exceptwith prior and express written permission of S.A.B.C.A.06/12/200433
Page 1 and 2: GSTP2-IMCMESTEC/Contract N° 13492/
Page 3 and 4: BRISC Architecture Overview Targete
Page 5 and 6: BRISC Architecture Overview Provide
Page 7 and 8: BRISC Architecture OverviewProgramb
Page 9 and 10: BRISC Architecture Overview On-chip
Page 11 and 12: BRISC Architecture Overview: Radiat
Page 17 and 18: Brisc Architecture Overview: ASIC T
Page 19 and 20: IMCM ASIC -HBRISC2- development log
Page 21 and 22: NOT USEDNOT USEDBXADD(0)BXADD(1)BXA
Page 23 and 24: Hbrisc2 Circuit Validation Strategy
Page 31: HBRISC2 application development pro
Page 36 and 37: Validation of the synthesiser The s
Page 38 and 39: The macro library The macros are cl
Page 40 and 41: The unit test tool Total_nw is a to
Page 42 and 43: Validation of the Simulink library
Page 44 and 45: IMCM Demonstration Application The
Page 46 and 47: IMCM Demonstration Application The
Page 48 and 49: VEGA TVC IPDUAVUMZ 9Z 23P 80EM TVC
Page 50 and 51: GSTP3 HPEA & GSTP4 Reaction Sphere,
Page 52: IMCM ConclusionHBRISC2 and its deve

hbrisc2 - Microelectronics

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