hbrisc2 - Microelectronics

BRISC Architecture Overview: Radiation Effects BRISC SEU-hardened architecture: instruction/data SRAM protectionProgrambus46/INSTRUCTION REGISTERON-CHIP SEUERRORDETECTION/CORRECTIONUNITUnit AGLOBALREGISTERSREGISTERBANKFLOATINGPOINTUNITADCinterfaceI/OinterfaceINSTRUCTIONDECODERGLOBALREGISTERSREGISTERBANKFLOATINGPOINTUNITCRCcheck 32+8Unit BON-CHIP MEMORYSEU ERRORCORRECTIONUNITGLOBALREGISTERSFIXED POINTARITHMETICUNITRIOUnit SURPADON-CHIP PERIPHERALINTERFACEmotorPWMHBRISC2COREPeripheralbusexcitationPWMSerialFast link 16ADDRESSREGISTERINSTRUCTIONSEQUENCERBOOTROMREGISTERSSEUDETECTION/CORRECTIONUNITSerial port(SPI)softwaretimerAddressbus4/• “LIVE” CORRECTION BEFOREINSTRUCTION DECODING• AUTOMATIC SRAM CORRECTIONON HBRISC2 STOLEN CYCLES• MODIFIED HAMMING CODE detects and corrects all 1-bit errors detects all 2-bit errors detects part of multiple-bit errors• NO ADDED DELAY DURINGINSTRUCTION FETCH• HARDWARE REPORTINGHBRISC2PERIPHERAL 18 6 2 1TN0342-Iss10.pptAll right reserved: Disclosure to third parties of this document or any part thereof, or the use of any information contained therein for purposes other than provided for by this document, is not permitted exceptwith prior and express written permission of S.A.B.C.A.06/12/200413