INDUSTRIAL GRADE CPU BOARD User’ s Guide

AR-B1479 User’s Guide
2.2 64-BIT SDRAM UMA CONTROLLER
! 64-bit data bus.
! Up to100 MHz SDRAM clock speed.
! Integrated system memory, graphic frame memory and video frame memory.
! Supports 2MB up to 128 MB system memory
! Supports 16-, 64-, and 128-Mbit SDRAMs.
! Supports 8, 16, 32, 64, and 128 MB DIMMs.
! Supports buffered, non-buffered, and registered DIMMs.
! Four-line write buffers for CPU to SDRAM and PCI to SDRAM cycles.
! Four0line read prefetch buffers for PCI masters.
! Programmable latency
! Programmable timing for SDRAM parameters.
! Supports –8, -10, -12, -13, -15 memory parts.
! Supports memory hole between 1 MB and 8 MB for PCI/ISA busses.
The SDRAM controller only supports 64 bit wide Memory Banks.
Four Memory Banks (if DIMMS are used; Single sided or two doubled-sided DIMMs) are supported in the following
configurations.
Memory
Bank size
Number Organization
1Mx64 4 1Mx16
2Mx64 8 2Mx8
4Mx64 16 4Mx4
4Mx64 4 2Mx16x2
8Mx64 8 4Mx8x2
16xM64 16 8Nx4x2
4Mx64 4 1Mx16x4
8Mx64 8 2Mx8x4
32Mx64 16 4Mx4x4
16Mx64 8 2Mx16x2
32Mx64 16 4Mx8x4
Memory configurations
Device
Size
16Mbits
64Mbits
128Mbits
The SDRAM Controller supports buffered or unbuffered SDRAM but not EDO or FPM modes. SDRAMs must
support Full Page Mode Type access.
The STPC Memory Controller provides various programmable SDRAM parameters to allow the SDRAM interface
to be optimized for different processor bus speeds SDRAM grades and CAS Latency
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