Datascope Passport - Mindray
Datascope Passport - Mindray
Datascope Passport - Mindray
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Front End Module Theory of Operation<br />
2.2.15 Data Packets<br />
The other timer channel pins (Port GP 5..7) are unused, and should be configured as outputs,<br />
to eliminate the need for termination. However, the associated internal timer channels may<br />
be used for software purposes, such as the 2 ms data acquisition interrupt, flash<br />
programming timer, etc.<br />
The data communications via the UART and communication isolation circuits are in the form<br />
of bursts, or packets, of data.<br />
The SCI is used to support the RS-485 module bus interface, operating at 500 kbaud. The<br />
SCI is operated in the 9 bit mode. In the module bus protocol, ninth bits are set only when a<br />
module address is transmitted. Most of the time, the SCI is operated in the Address Mark<br />
Wake-Up mode. In this mode, it ignores all characters without the ninth bit set. Each time an<br />
address is sent on the module bus, the receiver will generate an interrupt on this character.<br />
Software must rapidly evaluate this character to determine if it matches the module address.<br />
If it does not match, the SCI mode remains unchanged, and the bus continues to be<br />
monitored for address characters only. However, if there is a match, the SCI must<br />
immediately be placed in the normal receive mode, so that the rest of the poll packet can be<br />
received and buffered. The CRC is evaluated during reception. If the poll packet CRC is<br />
valid, the transmitter is enabled, and SCI is used to transmit a pre-buffered response packet.<br />
Following this packet, the transmitter is disabled, and the SCI is returned to the Address Mark<br />
Wake-Up mode. Control of the transmitter is by means of peripheral select 3 (Port PQS 6),<br />
which is brought low to enable the RS-485 transmitter.<br />
Because of the high data transmission speed, each of the phases of module bus<br />
communications is best handled through a separate ISR, with the interrupt vector being<br />
changed for each phase. This will result in faster response than could be achieved in a single<br />
ISR with conditional code. The SCI must be the highest priority peripheral interrupt in the<br />
system, due to the high communication speed.<br />
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