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2. Fault Analysis of the Rule 30 Stream Cipher<br />

This section introduces our fault attack on the Rule 30 Stream Cipher, <strong>de</strong>scribed earlier in<br />

section 1.4. For sake of feasibility, the following assumptions are ma<strong>de</strong>:<br />

• The adversary knows a sequence of n/2 + 1 bits extracted from the register of the<br />

cryptographic <strong>de</strong>vice. I.e., he/she knows a t i, for t = 1, . . . , n/2+1. This sequence<br />

is stored in the central column of a matrix A<br />

• The adversary has the capability of changing the content of chosen areas of the<br />

register, i.e., of flipping their stored value. He/she can also reset the <strong>de</strong>vice.<br />

This cryptanalytic technique is divi<strong>de</strong>d into 3 steps (or phases). In the first step,<br />

we <strong>de</strong>termine the bits of the two columns adjacent to the central column. In the second<br />

step, we proceed with the <strong>de</strong>termination of the bits on the right si<strong>de</strong> of the central column.<br />

In step 3, we <strong>de</strong>termine the bits on the left si<strong>de</strong> of the central column.<br />

As will be shown, as the attack goes on, the actions taken by the cryptanalyst will<br />

<strong>de</strong>pend on the observed configuration of the cells. The method is <strong>de</strong>scribed below.<br />

STEP 1: Determination of the bits of the two columns adjacent to the central column.<br />

This step consists of provoking a fault into the register for each known pair of bits. It is<br />

possible to <strong>de</strong>termine the two pairs of bits adjacent to the central column.<br />

(<br />

a<br />

t−1<br />

i−1<br />

a t−1<br />

i<br />

a t−1<br />

i+1<br />

x a t i x<br />

)<br />

Configuration 1.1<br />

(<br />

a<br />

t−1<br />

i−1<br />

a t−1<br />

i<br />

a t−1<br />

i+1<br />

x a t i x<br />

)<br />

=<br />

(<br />

a<br />

t−1<br />

i−1 0 a t−1<br />

i+1<br />

x 0 x<br />

)<br />

This configuration is only possible if a t−1<br />

i−1 = a t−1<br />

i+1 = 1 or a t−1<br />

i−1 = a t−1<br />

i+1 = 0. If the<br />

attacker flips the bit a t−1<br />

i and then recomputes the bit a t i, there will be two possibilities:<br />

• If a t i = 0, then a t−1<br />

i−1 = a t−1<br />

i+1 = 1<br />

• If a t i = 1, then a t−1<br />

i−1 = a t−1<br />

i+1 = 0<br />

Configuration 1.2<br />

(<br />

a<br />

t−1<br />

i−1<br />

a t−1<br />

i<br />

a t−1<br />

i+1<br />

x a t i x<br />

)<br />

=<br />

(<br />

a<br />

t−1<br />

i−1 0 a t−1<br />

i+1<br />

x 1 x<br />

)<br />

This configuration is only possible if a t−1<br />

i−1 = 0 and a t−1<br />

i+1 = 1 or a t−1<br />

i−1 = 1 and<br />

a t−1<br />

i+1 = 0. If the attacker flips the bit a t−1<br />

i and then recomputes the bit a t i, there will be two<br />

possibilities:<br />

• If a t i = 1, then a t−1<br />

i−1 = 0 and a t−1<br />

i+1 = 1<br />

• If a t i = 0, then a t−1<br />

i−1 = 1 and a t−1<br />

i+1 = 0<br />

87

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