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001 ccn00332236 006 m f d 007 cr cn ---uuauu 008 110419s2011 nyua fob 001 0 eng d 020 $a0071773339 020 $z9780071753791 (print) 035 $a(Sirsi) a332236 050 4$aTK7874.53$b.L38 2011 082 04$a621.381/046$222 100 1 $aLau, John H. 245 10$aReliability of RoHS-Compliant 2D and 3D IC interconnects$h[electronic resource] /$cJohn H. Lau. 260 $aNew York :$bMcGraw-Hill,$c[2011] 300 $a1 electronic text (xxix, 606 p.) :$bill. (some col.). 490 1 $aMcGraw-Hill's AccessEngineering 490 1 $aElectronic engineering 588 $aDescription based on cover image and table of contents, viewed on April 19, 2011. 500 $aPrint version c2011. 504 $aIncludes bibliographical references and index. 530 $aAlso issued in print and PDF versions. 520 $a"Unique global coverage of RoHS-compliant materials for electronics manufacturing and for packaging assembly and semiconductor integration Reliability of RoHS-Compliant 2D and 3D IC Interconnects provides comprehensive details on RoHS-compliant electronics packaging solder interconnects. This authoritative guide aids in developing innovative, high-performance, costeffective, and reliable lead-free interconnects for electronics and optoelectronic products. Reliability of RoHS-Compliant 2D and 3D IC Interconnects Covers chip-level interconnect reliability, first- and second-level interconnect reliability, and 3D IC integration interconnect reliability Addresses challenging problems created by increasing interest in lead-free interconnect reliability of 3D packaging and 3D IC integration Provides information fundamental to research and development of design (mechanical, optical, electrical, and thermal); materials; process; manufacturing; testing; and reliability for lead-free interconnects in RoHS-compliant electronics products Removes road blocks to, avoids unnecessary false starts in, and accelerates design, materials, and process development in packaging technology In-depth details: Introduction to RoHS Compliant Semiconductor and Packaging Technologies; Reliability Engineering of Lead-Free Interconnects; Notes on Failure Criterion; Reliability of 1657-Pin CCGA Lead-Free Solder Joints; Reliability of PBGA Lead-Free Solder Joints; Reliability of LED Lead-Free Interconnects; Reliability of VCSEL Lead-Free Interconnects; Reliability of Low-Temperature Lead-Free (SnBiAg) Solder Joints; Reliability of Lead-Free (SACX) Solder Joints; Chip-to-Wafer (C2W) Lead-Free Interconnect Reliability; Waferto-Wafer (W2W) Lead-Free Interconnect Reliability; Through-Silicon-Via (TSV) Interposer Lead- Free Interconnect Reliability; Electromigration of Lead-Free Microbumps for 3D IC Integrations; Effects of Dwell-Time and Ramp-Rates on SAC Thermal Cycling Test Results; Effects of High Strain Rate (Impact) on SAC Solder Bumps; Effects of Voids on Solder Joints Reliability"--Provided by publisher. 520 $a"Reliability of RoHS-Compliant 2D and 3D IC Interconnects provides comprehensive coverage of RoHS-compliant electronics packaging solder interconnects. RoHS--the restriction of the use of certain hazardous substances in electrical and electronic equipment--is law in the EU, China, Japan, Korea, Canada, Australia, California, etc. RoHS bans lead and five other materials; thus, in order to ship electrical products to these regions and countries, products must be lead-free. The material in this book aids in developing innovative, high-performance, cost-effective, and reliable lead-free interconnects for electronics and optoelectronic products"--Provided by publisher. 650 0$aInterconnects (Integrated circuit technology)$xReliability. 650 0$aGreen technology$xReliability. 655 0$aElectronic books. 655 0$aInternet resources. 740 02$aIntroduction to RoHS-compliant semiconductor and packaging technologies. 740 02$aReliability engineering of lead-free interconnects. 740 02$aNotes on failure criteria. 740 02$aReliability of 1657-Pin CCGA lead-free solder joints. 740 02$aReliability of PBGA lead-free solder joints (with and without Underfills). 740 02$aReliability of LED lead-free interconnects. 740 02$aReliability of VCSEL lead-free interconnects. 740 02$aReliability of low-temperature lead-free (SnBiAg) solder joints. 740 02$aReliability of lead-free (SACX) solder joints. 740 02$aChip-to-wafer (C2W) bonding and lead-free interconnect reliability. 740 02$aWafer-to-wafer (W2W) bonding and lead-free interconnect reliability.
740 02$aThrough-silicon-via (TSV) interposer reliability. 740 02$aElectromigration of lead-free microbumps for 3-D IC integration. 740 02$aEffects of dwell[-] time and ramp[-] rate[s] on SAC thermal cycling test results. 740 02$aEffects of high strain rate (impact) on SAC solder balls/bumps. 740 02$aEffects of voids on solder joint[s] reliability. 830 0$aMcGraw-Hill's AccessEngineering. 830 0$aMcGraw-Hill electronic engineering series. 856 40$uhttp://accessengineeringlibrary.com/browse/reliability-of-rohs-compliant-2d-and-3d-icinterconnects$zSubscription required 949 $aTK 7874.53 .L38$wLC$c1$i332236-1001$d12/30/2011$lMAIN$mMGH$q2$rY$sY$tWEB$u4/19/2011$xENG 997 $a(c)2011 Cassidy Cataloguing Services, Inc. 000 02637cam 2200613 a 4500 001 ccn00334936 006 m f d 007 cr cn ---uuauu 008 110608s2011 nyua fob 001 0 eng d 010 $z 2007019390 020 $a0071549234 020 $z0071493751 (print) 020 $z9780071493758 (print) 035 $a(Sirsi) a334936 050 4$aTK7872.P38$bB475 2007 082 04$a621.3815/364$222 100 1 $aBest, Roland E. 245 10$aPhase-locked loops$h[electronic resource] :$bdesign, simulation, and applications /$cRoland E. Best. 250 $a6th ed. 260 $aNew York :$bMcGraw-Hill,$c[2011] 300 $a1 electronic text (xii, 490 p.) :$bill. 490 1 $aMcGraw-Hill's AccessEngineering 588 $aDescription based on cover image and table of contents, viewed on June 8, 2011. 500 $aPrint version c2007. 504 $aIncludes bibliographical references (p. 473-475) and index. 505 0 $uhttp://www.loc.gov/catdir/toc/ecip0717/2007019390.html 530 $aAlso issued in print and PDF versions. 545 0 $aContributor biographical information$uhttp://www.loc.gov/catdir/enhancements/fy0726/2007019390-b.html 650 0$aPhase-locked loops. 655 0$aElectronic books. 655 0$aInternet resources. 740 02$aIntroduction to PLLS. 740 02$aMixed-signal PLL building blocks. 740 02$aMixed-signal analysis. 740 02$aPLL performance in the presence of noise. 740 02$aDesign procedure for mixed-signal PLL. 740 02$aMixed-signal PLL applications part 1: integer-n frequency synthesizers. 740 02$aMixed-signal PLL applications part 2: fractional-n frequency synthesizers. 740 02$aMixed-signal PLL applications part 3: miscellaneous applications. 740 02$aHigher-order loops. 740 02$aComputer-aided design and simulation of mixed-signal PLLS. 740 02$aAll-digital PLLS (ADPLLS). 740 02$aComputer-aided design and simulation of ADPLLS. 740 02$aSoftware PLL (SPLL). 740 02$aPLL in communications. 740 02$aSearching PLL integrated circuits. 740 02$aPull-in process. 740 02$aLaplace transform. 740 02$aDigital filter basics. 740 02$aMeasuring PLL parameters. 830 0$aMcGraw-Hill's AccessEngineering. 856 40$uhttp://accessengineeringlibrary.com/browse/phase-locked-loops-design-simulation-andapplications-sixth-edition$zSubscription required 949 $aTK 7872 .P38 B475$wLC$c1$i334936-1001$d12/30/2011$lMAIN$mMGH$q2$rY$sY$tWEB$u6/8/2011$xENG 997 $a(c)2011 Cassidy Cataloguing Services, Inc.
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Page 83 and 84: 650 0$aBiomedical engineering. 650
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Page 103 and 104: 740 02$aAlternating-current circuit
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process variations -- ch. 9. Procur
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analysis of components -- ch. 19. S
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