Chapter 08 Power, Reset, and Clock Management (PRCM).pdf

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www.ti.com Power, Reset, and Clock Management Table 8-12. Power Domain Control and Status Registers (continued) Register/Bit Field Type Description PM__PWRSTST[5:4] MEMSTATEST 8.1.4.2.1 Power-Management Techniques Identifies the current state of the memory Status area in the power domain. It can be OFF, ON, or RETENTION The following section describes the state-of-the-art power-management techniques supported by the device. 8.1.4.2.1.1 Adaptive Voltage Scaling AVS is a power-management technique based in Smart Reflex that is used for automatic control of the operating voltages of the device to reduce active power consumption. With Smart Reflex, power-supply voltage is adapted to silicon performance, either statically (based on performance points predefined in the manufacturing process of a given device) or dynamically (based on the temperature-induced real-time performance of the device). A comparison of these predefined performance points to the real-time on-chip measured performance determines whether to raise or lower the power-supply voltage. AVS achieves the optimal performance/power trade-off for all devices across the technology process spectrum and across temperature variation. The device voltage is automatically adapted to maintain performance of the device 8.1.4.3 Power Modes The following power modes are for easy reference applicable for typical use cases. The design does not restrict these to be the only modes. In order of the lowest power to the highest power, these modes are named RTC-Only, DeepSleep0, DeepSleep1, DeepSleep2, Standby and Active. All voltage supplies must be maintained for the each of the Deep Sleep, Standby and Active modes. In Active mode, all power domains are ON. In RTC mode, only the supplies to the RTC subsystem are supplied. The contents of SDRAM are preserved in any of the Deep Sleep/Standby modes. This is done by placing SDRAM in self-refresh prior to entering Deep Sleep. Use CasePower Mode Application state Table 8-13. Typical Power Modes Only RTC voltage domain is alive. RTC-Only Optionally, SDRAM can be kept in selfrefresh which will reduce the boot time. DeepSleep0 Power Domain States& Supply Voltages VDD_MPU = 0v VDD_CORE = 0v VDDS_RTC supply is active. Optionally, IO supplies can be left ON PD_PER peripheral & CortexA8 / MPU register information will be lost. On-chip peripheral register (context) information of PD_PER domain needs to be saved by application to SDRAM before Master Oscillator = OFF VDD_MPU = 0.95v VDD_CORE = 0.95v PD_WKUP = ON entering this mode. PD_MPU = OFF SDRAM is in self-refresh. For wakeup, boot ROM executes and branches to peripheral context restore followed by system resume. PD_PER = OFF PD_GFX = OFF All IO supplies & RTC supplies are ON On-chip peripheral registers are Master Oscillator = OFF preserved. VDD_MPU = 0.95v CortexA8 context/registers are lost and VDD_CORE = 0.95v DeepSleep1 hence application needs to save them to MPU Subsystem or L3 OCMC RAM or SDRAM before entering DeepSleep. PD_WKUP = ON PD_MPU = OFF SDRAM is in self-refresh. PD_PER = ON For wakeup, boot ROM executes and PD_GFX = OFF branch to system resume. All IO supplies & RTC supplies are ON SPRUH73E–October 2011–Revised May 2012 Power, Reset, and Clock Management (PRCM) Submit Documentation Feedback Copyright © 2011–2012, Texas Instruments Incorporated 641
Power, Reset, and Clock Management www.ti.com Use CasePower Mode Application state Table 8-13. Typical Power Modes (continued) Power Domain States& Supply Voltages DeepSleep2 Everything is preserved including SDRAM. Master Oscillator = OFF VDD_MPU = 0.95v VDD_CORE = 0.95v PD_WKUP = ON PD_MPU = ON PD_PER = ON PD_GFX = OFF All IO supplies & RTC supplies are ON Master Oscillator = ON One PLL is ON. VDD_MPU = 0.95v VDD_CORE = OPP50 PD_WKUP = ON Everything is preserved including SDRAM. PD_MPU = ON Standby Only required module clocks are enabled, rest are clock gated. PD_PER = ON PD_GFX = OFF All IO supplies & RTC supplies are ON If more PLLs /power domains/ modules are required, the power will increase accordingly. Active All Features 8.1.4.3.1 Active Master Oscillator = ON One or more PLLs are ON VDD_MPU = ON VDD_CORE = ON PD_WKUP = ON PD_MPU = ON PD_PER = ON PD_GGX = ON In Active mode, the supply to all voltage rails must be maintained. All power domains come up in ON state and the device is fully functional. 8.1.4.3.2 Standby In Standby mode, the supply to all voltage rails must be maintained. The power consumption can be minimized if the supply voltage placed at its minimum operating voltage. Using Software the required PLL’s are made active depending upon wakeup or use case requirements and the rest are placed in low power bypass modes. All non-essential IP blocks are powered down. A peripheral interrupt to CortexM3, will cause it to un-clock gate the A8 after which A8 services the pending interrupt. SDRAM contents are preserved. This is useful for quick standby/resume kind of application. 8.1.4.3.3 Deepsleep0 In DeepSleep0 mode, the supply to all voltage rails are maintained, only the PD_RTC and PD_WKUP power domains are ON. The master crystal oscillator is disabled. PD_MPU is OFF. The contents of OCMC RAM are preserved. Additionally the contents of the SDRAM are preserved by placing the SDRAM in self-refresh. Activity on wake up peripherals via wake up events enables the master crystal oscillator using the oscillator control circuit. Also, the wake up events interrupt CortexM3. 642 Power, Reset, and Clock Management (PRCM) SPRUH73E–October 2011–Revised May 2012 Submit Documentation Feedback Copyright © 2011–2012, Texas Instruments Incorporated
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