Chapter 08 Power, Reset, and Clock Management (PRCM).pdf

www.ti.com Power, Reset, and Clock Management
8.1.12.1.1 CM_PER_L4LS_CLKSTCTRL Register (offset = 0h) [reset = C0102h]
CM_PER_L4LS_CLKSTCTRL is shown in Figure 8-22 and described in Table 8-28.
This register enables the domain power state transition. It controls the SW supervised clock domain state
transition between ON-PER and ON-INPER states. It also hold one status bit per clock input of the
domain.
Figure 8-22. CM_PER_L4LS_CLKSTCTRL Register
31 30 29 28 27 26 25 24
Reserved CLKACTIVITY_TIME CLKACTIVITY_TIME CLKACTIVITY_GPIO_ CLKACTIVITY_SPI_G CLKACTIVITY_I2C_F
R6_GCLK R5_GCLK 5_GDBCLK CLK CLK
R-0h R-0h R-0h R-0h R-0h R-0h
23 22 21 20 19 18 17 16
Reserved CLKACTIVITY_GPIO_ CLKACTIVITY_GPIO_ CLKACTIVITY_GPIO_ CLKACTIVITY_GPIO_ CLKACTIVITY_GPIO_ CLKACTIVITY_LCDC CLKACTIVITY_TIME
4_GDBCLK 3_GDBCLK 2_GDBCLK 1_GDBCLK 6_GDBCLK _GCLK R4_GCLK
R-0h R-0h R-0h R-0h R-1h R-1h R-0h R-0h
15 14 13 12 11 10 9 8
CLKACTIVITY_TIME CLKACTIVITY_TIME CLKACTIVITY_TIME Reserved CLKACTIVITY_CAN_ CLKACTIVITY_UART Reserved CLKACTIVITY_L4LS_
R3_GCLK R2_GCLK R7_GCLK CLK _GFCLK GCLK
R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-1h
7 6 5 4 3 2 1 0
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Reserved CLKTRCTRL
R-0h R/W-2h
Table 8-28. CM_PER_L4LS_CLKSTCTRL Register Field Descriptions
Bit Field Type Reset Description
31-29 Reserved R 0h
28 CLKACTIVITY_TIMER6_ R 0h This field indicates the state of the TIMER6 CLKTIMER clock in the
GCLK domain.
0x0 = Inact : Corresponding clock is gated
0x1 = Act : Corresponding clock is active
27 CLKACTIVITY_TIMER5_ R 0h This field indicates the state of the TIMER5 CLKTIMER clock in the
GCLK domain.
0x0 = Inact : Corresponding clock is gated
0x1 = Act : Corresponding clock is active
26 CLKACTIVITY_GPIO_5_ R 0h This field indicates the state of the GPIO5_GDBCLK clock in the
GDBCLK domain.
0x0 = Inact : Corresponding clock is gated
0x1 = Act : Corresponding clock is active
25 CLKACTIVITY_SPI_GCL R 0h This field indicates the state of the SPI_GCLK clock in the domain.
K
0x0 = Inact : Corresponding clock is gated
0x1 = Act : Corresponding clock is active
24 CLKACTIVITY_I2C_FCLK R 0h This field indicates the state of the I2C _FCLK clock in the domain.
23 Reserved R 0h
0x0 = Inact : Corresponding clock is gated
0x1 = Act : Corresponding clock is active
22 CLKACTIVITY_GPIO_4_ R 0h This field indicates the state of the GPIO4_GDBCLK clock in the
GDBCLK domain.
0x0 = Inact : Corresponding clock is gated
0x1 = Act : Corresponding clock is active
SPRUH73E–October 2011–Revised May 2012 Power, Reset, and Clock Management (PRCM)
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