Chapter 08 Power, Reset, and Clock Management (PRCM).pdf

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www.ti.com Power, Reset, and Clock Management Table 8-1. Master Module Standby-Mode Settings (continued) Standby Mode Value Selected Mode Description 0x2 Smart-standby The module asserts the standby request based on its internal activity status. The standby signal is asserted only when all ongoing transactions are complete and the module is idled. The PRCM module can then gate the clocks to the module. The module asserts the standby request based on its internal activity status. The standby signal is asserted only when all ongoing transactions are complete and the module is idle. The PRCM module can 0x3 Smart-standbywakeup-capable mode then gate the clocks to the module. The module may generate (master-related) wake-up events when in STANDBY state. The mode is relevant only if the appropriate module mwakeup output is implemented. The standby status of a master module is indicated by the CM___CLKCTRL[x]. STBYST bit in the PRCM module. 8.1.3.2.2 Slave Idle Protocol Table 8-2. Master Module Standby Status STBYST Bit Value Description 0x0 The module is functional. 0x1 The module is in standby mode This hardware protocol allows the PRCM module to control the state of a slave module. The PRCM module informs the slave module, through assertion of an idle request, when its clocks (interface and functional) can be gated. The slave can then acknowledge the request from the PRCM module and the PRCM module is then allowed to gate the clocks to the module. A slave module is said to be in IDLE state when its clocks are gated by the PRCM module. Similarly, an idled slave module may need to be wakened because of a service request from a master module or as a result of an event (called a wake-up event; for example, interrupt or DMA request) received by the slave module. In this situation the PRCM module enables the clocks to the module and then deasserts the idle request to signal the module to wake up. Although the protocol is completely hardware-controlled, software must configure the clockmanagement behavior for the slave module. This is done by setting the module register bit field _SYSCONFIG. SIDLEMODE or _SYSCONFIG. IDLEMODE. The behavior, listed in the Idle Mode Value column, must be configured by software. Table 8-3. Module Idle Mode Settings Idle Mode Value Selected Mode Description 0x0 Force-idle The module unconditionally acknowledges the idle request from the PRCM module, regardless of its internal operations. This mode must be used carefully because it does not prevent the loss of data at the time the clock is switched off. The module never acknowledges any idle request from the PRCM module. This mode is safe from a module point of view because it ensures that the clocks remain 0x1 No-idle active. However, it is not efficient from a power-saving perspective because it does not allow the PRCM module output clock to be shut off, and thus the power domain to be set to a lower power state. SPRUH73E–October 2011–Revised May 2012 Power, Reset, and Clock Management (PRCM) Submit Documentation Feedback Copyright © 2011–2012, Texas Instruments Incorporated 635
Power, Reset, and Clock Management www.ti.com Table 8-3. Module Idle Mode Settings (continued) Idle Mode Value Selected Mode Description 0x2 Smart-idle The module acknowledges the idle request basing its decision on its internal activity. Namely, the acknowledge signal is asserted only when all pending transactions, interrupts, or direct memory access (DMA) requests are processed. This is the best approach to efficient system power management. The module acknowledges the idle request basing its decision on its internal wakeup-capable mode activity. Namely, the acknowledge signal is asserted only when all pending transactions, interrupts, or DMA requests are processed. This is 0x3 Smart-idle wakeup-capable mode the best approach to efficient system power management. The module may generate (IRQ- or DMA-request-related) wake-up events when in IDLE state. The mode is relevant only if the appropriate module swakeup output(s) is implemented. The idle status of a slave module is indicated by the CM___CLKCTRL[x] IDLEST bit field in the PRCM module. Table 8-4. Idle States for a Slave Module IDLEST Bit VALUE Idle Status Description 0x0 Functional 0x1 In transition The module is fully functional.The interface and functional clocks are active. The module is performing a wake-up or a sleep transition The module interface clock is idled. The 0x2 Interface idle module may remain functional if using a separate functional clock 0x3 Full idle The module is fully idle. The interface and functional clocks are gated. For the idle protocol management on the PRCM module side, the behavior of the PRCM module is configured in the CM___CLKCTRL[x] MODULEMODE bit field. Based on the configured behavior, the PRCM module asserts the idle request to the module unconditionally (that is, immediately when the software requests). Table 8-5. Slave Module Mode Settings in PRCM MODULEMODE Bit VALUE Selected Mode Description 0x0 Disabled 0x1 Reserved NA The PRCM module unconditionally asserts the module idle request. This request applies to the gating of the functional and interface clocks to the module. If acknowledged by the module, the PRCM module can gate all clocks to the module (that is, the module is completely disabled).. 636 Power, Reset, and Clock Management (PRCM) SPRUH73E–October 2011–Revised May 2012 Submit Documentation Feedback Copyright © 2011–2012, Texas Instruments Incorporated
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