Chapter 08 Power, Reset, and Clock Management (PRCM).pdf

www.ti.com Power, Reset, and Clock Management
All clock outputs of the DPLL can be gated. The Control module provides the DPLL with a clock gating
control signal to enable or disable the clock, and the DPLL provides the PRCM module with a clock
activity status signal to let the PRCM module hardware know when the clock is effectively running or
effectively gated. Output clock gating control for various clockouts:
CLKOUTEN/CLKOUTLDOEN/CLKDCOLDOEN.
8.1.6.4.1 Clock Functions
Table 8-17. Output Clocks in Locked Condition
Pin Name Frequency
CLKOUT [M /(N+1)] * CLKINP * [1/M2]
CLKOUTLDO [M /(N+1)] * CLKINP * [1/M2]
CLKDCOOUT [M /(N+1)] * CLKINP
Table 8-18. Output Clocks Before Lock and During Relock Modes
Pin Name Frequency Comments
CLKOUT
CLKDCOLDO LOW
CLKOUTLDO LOW
8.1.6.5 M2 and N2 Change On-the-Fly
CLKINP/(N2+1) ULOWCLKEN=’0’
CLKINPLOW ULOWCLKEN=’1’
The dividers M2 and N2 are designed to change on the fly and provide a glitch-free frequency switch from
the old to new frequencies. In other words, they can be changed while the PLL is in a locked condition,
without having to switch to bypass mode. A status toggle bit will give an indication if the new divisor was
accepted. These dividers can also be changed in bypass mode, and the new divisor value will be reflected
on output after the PLL relocks. For more details, see the PLL configuration procedures for each PLL.
8.1.6.6 Core PLL Description
The Core PLL provides the source for a majority of the device infrastructure and peripheral clocks. The
Core PLL comprises an ADPLLS with HSDIVIDER and additional dividers and muxes located in the
PRCM as shown in Figure 8-9.
SPRUH73E–October 2011–Revised May 2012 Power, Reset, and Clock Management (PRCM)
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