Chapter 08 Power, Reset, and Clock Management (PRCM).pdf

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www.ti.com Power, Reset, and Clock Management Master Osc (CLK_M_OSC) ALT_CLK1 ALT_CLK2 TEST.CDR (via P1500) Reset default = 0 0 1 2 Per PLL (ADPLLLJ) CLKINP Figure 8-10. Peripheral PLL Structure CLKDCOLDO CLKINPULOW ULOWCLKEN ULOWPRIORITY CLKOUT PER_CLKOUTM2 (192 MHz) Controls USB_PHY_CLK (960 MHz) PRCM /4 /2 /2 (96 MHz) (48 MHz) CLK_48 CLK_24 (32,768 Hz) ALT_CLKs are to be used for internal test purpose and should not be used in functional mode. *Reset default zero To USB PHY PRU_ICSS_UART_CLK MMC_CLK SPI_CLK UART_CLK I2C_CLK /732.4219 /366.2109 CLK_32KHZ CONTROL_CLK32K DIVRATIO_CTRL[0]* To DDR, Disp, MPU PLLs bypass clocking PRCM SGX clock mux The PLL is locked at 960 MHz. The PLL output is divided by the M2 divider to generate a 192-MHz CLKOUT. This clock is gated in the PRCM to form the PRU-ICSS UART clock. There is a /2 divider to create 96 MHz for MMC_CLK. The clock is also divided within the PRCM by a fixed /4 divider to create a 48-MHz clock for the SPI, UART and I2C modules. The 48-MHz clock is further divided by a fixed /2 divider and a fixed /732.4219 divider to create an accurate 32.768-KHz clock for Timer and debounce use. Clock Source PLL Lock frequency Table 8-22. Per PLL Typical Frequencies (MHz) Power-On-Reset / PLL Bypass OPP100 OPP50 DIV Value Freq DIV Value Freq (MHz) DIV Value Freq (MHz) PLL - - - 960 - 96 USB_PHY_CL CLKDCOLDO - Held Low - 960 - N/A K PER_CLKOU TM2 CLKOUT of ADPLLLJ CLKOUT uses PLL’s M2 Divider when PLL is locked and PLL’s N2 divider when PLL Bypass N2 is 0 on power-onreset Mstr Xtal/ (N2+1) 5 192 1 96 PER_CLKOU Mstr Xtal/ MMC_CLK 2 2 96 2 48 TM2 ((N2+1)*2) SPI_CLK, PER_CLKOU Mstr Xtal/ UART_CLK, 4 4 48 4 24 TM2 ((N2+1)*4) I2C_CLK CLK_24 CLK_48 2 CLK_48 /2 2 24 2 12 CLK_24 CLK_24 / CLK_32KHZ (output of 732.4219 732.4219 0.032768 366.2109 0.032768 CLK_48/2) SPRUH73E–October 2011–Revised May 2012 Power, Reset, and Clock Management (PRCM) Submit Documentation Feedback Copyright © 2011–2012, Texas Instruments Incorporated 0 1 657
Power, Reset, and Clock Management www.ti.com The ADPLLLJ module supports two different bypass modes via their internal MNBypass mode and their external Low Power Idle bypass mode. The PLLs are in the MNBypass mode after power-on reset and can be configured by software to enter Low Power Idle bypass mode for power-down. The PER PLL can use the Low Power Idle bypass mode. When the internal bypass mode is selected, the CLKOUT output is driven by CLKINP/(N2+1) where N2 is driven by the PRCM. CLKINP defaults to the master oscillator input (typically 24 MHz) 8.1.6.7.1 Configuring the Peripheral PLL The following steps detail how to configure the peripheral PLL. 1. Switch PLL to bypass mode by setting CM_CLKMODE_DPLL_PER.DPLL_EN to 0x4. 2. Wait for CM_IDLEST_DPLL_PER.ST_MN_BYPASS = 1 to ensure PLL is in bypass (CM_IDLEST_DPLL_PER.ST_DPLL_CLK should also change to 0 to denote the PLL is unlocked). 3. Configure Multiply and Divide values by setting CM_CLKSEL_DPLL_PER.DPLL_MULT and DPLL_DIV to the desired values. 4. Configure M2 divider by setting CM_DIV_M2_DPLL_PER.DPLL_CLKOUT_DIV to the desired value. 5. Switch over to lock mode by setting CM_CLKMODE_DPLL_PER.DPLL_EN to 0x7. 6. Wait for CM_IDLEST_DPLL_PER.ST_DPLL_CLK = 1 to ensure PLL is locked (CM_IDLEST_DPLL_PER.ST_MN_BYPASS should also change to 0 to denote the PLL is out of bypass mode). Note: M2 divider can also be changed on-the-fly (ie., there is no need to put the PLL in bypass and back to lock mode). After changing CM_DIV_M2_DPLL_PER.DPLL_CLKOUT_DIV, check CM_DIV_M2_DPLL_PER.DPLL_CLKOUT_DIVCHACK for a toggle (a change from 0 to 1 or 1 to 0) to see if the change was acknowledged by the PLL. 8.1.6.8 MPU PLL Description The Cortex A8 MPU subsystem includes an internal ADPLLS for generating the required Cortex A8 MPU clocks. This PLL is driven by the master oscillator output with control provided by PRCM registers. 658 Power, Reset, and Clock Management (PRCM) SPRUH73E–October 2011–Revised May 2012 Submit Documentation Feedback Copyright © 2011–2012, Texas Instruments Incorporated
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