Chapter 08 Power, Reset, and Clock Management (PRCM).pdf

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www.ti.com Power, Reset, and Clock Management 8.1.12 Clock Module Registers 8.1.12.1 CM_PER Registers Table 8-27 lists the memory-mapped registers for the CM_PER. All register offset addresses not listed in Table 8-27 should be considered as reserved locations and the register contents should not be modified. Table 8-27. CM_PER REGISTERS Offset Acronym Register Name Section 0h CM_PER_L4LS_CLKSTCTRL This register enables the domain power state transition. Section 8.1.12.1.1 It controls the SW supervised clock domain state transition between ON-PER and ON-INPER states. It also hold one status bit per clock input of the domain. 4h CM_PER_L3S_CLKSTCTRL This register enables the domain power state transition. Section 8.1.12.1.2 It controls the SW supervised clock domain state transition between ON-ACTIVE and ON-INACTIVE states. It also hold one status bit per clock input of the domain. Ch CM_PER_L3_CLKSTCTRL This register enables the domain power state transition. Section 8.1.12.1.3 It controls the SW supervised clock domain state transition between ON-ACTIVE and ON-INACTIVE states. It also hold one status bit per clock input of the domain. 14h CM_PER_CPGMAC0_CLKCTRL This register manages the CPSW clocks. Section 8.1.12.1.4 18h CM_PER_LCDC_CLKCTRL This register manages the LCD clocks. Section 8.1.12.1.5 1Ch CM_PER_USB0_CLKCTRL This register manages the USB clocks. Section 8.1.12.1.6 24h CM_PER_TPTC0_CLKCTRL This register manages the TPTC clocks. Section 8.1.12.1.7 28h CM_PER_EMIF_CLKCTRL This register manages the EMIF clocks. Section 8.1.12.1.8 2Ch CM_PER_OCMCRAM_CLKCTRL This register manages the OCMC clocks. Section 8.1.12.1.9 30h CM_PER_GPMC_CLKCTRL This register manages the GPMC clocks. Section 8.1.12.1.10 34h CM_PER_MCASP0_CLKCTRL This register manages the MCASP0 clocks. Section 8.1.12.1.11 38h CM_PER_UART5_CLKCTRL This register manages the UART5 clocks. Section 8.1.12.1.12 3Ch CM_PER_MMC0_CLKCTRL This register manages the MMC0 clocks. Section 8.1.12.1.13 40h CM_PER_ELM_CLKCTRL This register manages the ELM clocks. Section 8.1.12.1.14 44h CM_PER_I2C2_CLKCTRL This register manages the I2C2 clocks. Section 8.1.12.1.15 48h CM_PER_I2C1_CLKCTRL This register manages the I2C1 clocks. Section 8.1.12.1.16 4Ch CM_PER_SPI0_CLKCTRL This register manages the SPI0 clocks. Section 8.1.12.1.17 50h CM_PER_SPI1_CLKCTRL This register manages the SPI1 clocks. Section 8.1.12.1.18 60h CM_PER_L4LS_CLKCTRL This register manages the L4LS clocks. Section 8.1.12.1.19 64h CM_PER_L4FW_CLKCTRL This register manages the L4FW clocks. Section 8.1.12.1.20 68h CM_PER_MCASP1_CLKCTRL This register manages the MCASP1 clocks. Section 8.1.12.1.21 6Ch CM_PER_UART1_CLKCTRL This register manages the UART1 clocks. Section 8.1.12.1.22 70h CM_PER_UART2_CLKCTRL This register manages the UART2 clocks. Section 8.1.12.1.23 74h CM_PER_UART3_CLKCTRL This register manages the UART3 clocks. Section 8.1.12.1.24 78h CM_PER_UART4_CLKCTRL This register manages the UART4 clocks. Section 8.1.12.1.25 7Ch CM_PER_TIMER7_CLKCTRL This register manages the TIMER7 clocks. Section 8.1.12.1.26 80h CM_PER_TIMER2_CLKCTRL This register manages the TIMER2 clocks. Section 8.1.12.1.27 84h CM_PER_TIMER3_CLKCTRL This register manages the TIMER3 clocks. Section 8.1.12.1.28 88h CM_PER_TIMER4_CLKCTRL This register manages the TIMER4 clocks. Section 8.1.12.1.29 ACh CM_PER_GPIO1_CLKCTRL This register manages the GPIO1 clocks. Section 8.1.12.1.30 B0h CM_PER_GPIO2_CLKCTRL This register manages the GPIO2 clocks. Section 8.1.12.1.31 B4h CM_PER_GPIO3_CLKCTRL This register manages the GPIO3 clocks. Section 8.1.12.1.32 BCh CM_PER_TPCC_CLKCTRL This register manages the TPCC clocks. Section 8.1.12.1.33 C0h CM_PER_DCAN0_CLKCTRL This register manages the DCAN0 clocks. Section 8.1.12.1.34 SPRUH73E–October 2011–Revised May 2012 Power, Reset, and Clock Management (PRCM) Submit Documentation Feedback Copyright © 2011–2012, Texas Instruments Incorporated 677
Power, Reset, and Clock Management www.ti.com Table 8-27. CM_PER REGISTERS (continued) Offset Acronym Register Name Section C4h CM_PER_DCAN1_CLKCTRL This register manages the DCAN1 clocks. Section 8.1.12.1.35 CCh CM_PER_EPWMSS1_CLKCTRL This register manages the PWMSS1 clocks. Section 8.1.12.1.36 D4h CM_PER_EPWMSS0_CLKCTRL This register manages the PWMSS0 clocks. Section 8.1.12.1.37 D8h CM_PER_EPWMSS2_CLKCTRL This register manages the PWMSS2 clocks. Section 8.1.12.1.38 DCh CM_PER_L3_INSTR_CLKCTRL This register manages the L3 INSTR clocks. Section 8.1.12.1.39 E0h CM_PER_L3_CLKCTRL This register manages the L3 Interconnect clocks. Section 8.1.12.1.40 E4h CM_PER_IEEE5000_CLKCTRL This register manages the IEEE1500 clocks. Section 8.1.12.1.41 E8h CM_PER_PRU_ICSS_CLKCTRL This register manages the PRU-ICSS clocks. Section 8.1.12.1.42 ECh CM_PER_TIMER5_CLKCTRL This register manages the TIMER5 clocks. Section 8.1.12.1.43 F0h CM_PER_TIMER6_CLKCTRL This register manages the TIMER6 clocks. Section 8.1.12.1.44 F4h CM_PER_MMC1_CLKCTRL This register manages the MMC1 clocks. Section 8.1.12.1.45 F8h CM_PER_MMC2_CLKCTRL This register manages the MMC2 clocks. Section 8.1.12.1.46 FCh CM_PER_TPTC1_CLKCTRL This register manages the TPTC1 clocks. Section 8.1.12.1.47 100h CM_PER_TPTC2_CLKCTRL This register manages the TPTC2 clocks. Section 8.1.12.1.48 10Ch CM_PER_SPINLOCK_CLKCTRL This register manages the SPINLOCK clocks. Section 8.1.12.1.49 110h CM_PER_MAILBOX0_CLKCTRL This register manages the MAILBOX0 clocks. Section 8.1.12.1.50 11Ch CM_PER_L4HS_CLKSTCTRL This register enables the domain power state transition. Section 8.1.12.1.51 It controls the SW supervised clock domain state transition between ON-ACTIVE and ON-INACTIVE states. It also hold one status bit per clock input of the domain. 120h CM_PER_L4HS_CLKCTRL This register manages the L4 Fast clocks. Section 8.1.12.1.52 12Ch CM_PER_OCPWP_L3_CLKSTCT This register enables the domain power state transition. Section 8.1.12.1.53 RL It controls the SW supervised clock domain state transition between ON-ACTIVE and ON-INACTIVE states. It also hold one status bit per clock input of the domain. 130h CM_PER_OCPWP_CLKCTRL This register manages the OCPWP clocks. Section 8.1.12.1.54 140h CM_PER_PRU_ICSS_CLKSTCTR This register enables the clock domain state transition. Section 8.1.12.1.55 L It controls the SW supervised clock domain state transition between ON-ACTIVE and ON-INACTIVE states. It also hold one status bit per clock input of the domain. 144h CM_PER_CPSW_CLKSTCTRL This register enables the clock domain state transition. Section 8.1.12.1.56 It controls the SW supervised clock domain state transition between ON-ACTIVE and ON-INACTIVE states. It also hold one status bit per clock input of the domain. 148h CM_PER_LCDC_CLKSTCTRL This register enables the clock domain state transition. Section 8.1.12.1.57 It controls the SW supervised clock domain state transition between ON-ACTIVE and ON-INACTIVE states. It also hold one status bit per clock input of the domain. 14Ch CM_PER_CLKDIV32K_CLKCTRL This register manages the CLKDIV32K clocks. Section 8.1.12.1.58 150h CM_PER_CLK_24MHZ_CLKSTCT This register enables the clock domain state transition. Section 8.1.12.1.59 RL It controls the SW supervised clock domain state transition between ON-ACTIVE and ON-INACTIVE states. It also hold one status bit per clock input of the domain. 678 Power, Reset, and Clock Management (PRCM) SPRUH73E–October 2011–Revised May 2012 Submit Documentation Feedback Copyright © 2011–2012, Texas Instruments Incorporated
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