Chapter 08 Power, Reset, and Clock Management (PRCM).pdf

More documents

Recommendations

Info

www.ti.com Power, Reset, and Clock Management Table 8-19. PLL and Clock Frequences Mux Select Register Bit Section 9.2.4.4 A PRCM.CLKSEL_GFX_FCLK[1] B PRCM.CLKSEL_GFX_FCLK[0] C PRCM.CLKSEL_PRU-ICSS_OCP_CLK[0] D PRCM.CM_CPTS_RFT_CLKSEL[0] E TEST.CDR (via P1500) Table 8-20 gives the typical PLL and clock frequencies. The HSDIVIDER is used to generate three divided clocks M4, M5 & M6. M4 & M5 are nominally 200 & 250 MHz, respectively. CLOCK Source CLKDCOLDO (PLL Lock frequency) Table 8-20. Core PLL Typical Frequencies (MHz) Power-On-Reset / HSDIVIDER Bypass OPP100 OPP50 (1) DIV Freq DIV Value Freq (MHz) DIV Value Freq (MHz) APLLS - - - 2000 - 100 HSDIVIDER- CORE_CLKOUTM4 - Mstr Xtal 10 200 1 100 M4 L3F_CLK, L4F_CLK, PRU-ICSS IEP CLK, DebugSS clka, SGX.MEMCLK, SGX.SYSCLK CORE_CLKO UTM4 - Mstr Xtal - 200 - 100 L4_PER, L4_WKUP CORE_CLKO UTM4 2 Mstr Xtal / 2 2 100 2 50 SGX CORECLK CORE_CLKO UTM4 1 Mstr Xtal 1 2 200 100 1 2 100 50 HSDIVIDER- CORE_CLKOUTM5 - Mstr Xtal 8 250 1 100 M5 MHZ_250_CLK (Gigabit CORE_CLKO RGMII) UTM5 - NA - 250 - NA MHZ_125_CLK CORE_CLKO (Ethernet Switch Bus 2 Mstr Xtal / 2 2 125 2 50 UTM5 Clk) MHZ_50_CLK (100 CORE_CLKO mbps RGMII or 10/100 5 Mstr Xtal / 5 5 50 2 50 UTM5 RMII) MHZ_5_CLK (10 mbps RGMII) MHZ_50_CLK 10 Mstr Xtal / 50 10 5 10 5 HSDIVIDER CORE_CLKOUTM6 - Mstr Xtal 2 500 1 100 M6 (1) Not all interfaces and peripheral modules are available in OPP50. For more information, see the device specific datasheet. The ADPLLS module supports two different bypass modes via their internal MNBypass mode and their external Low Power Idle bypass mode. The PLLs are in the MNBypass mode after power-on reset and can be configured by software to enter Low Power Idle bypass mode for power-down. When the Core PLL is configured in bypass mode, the HSDIVIDER enters bypass mode and the CLKINBYPASS input is driven on the M4, M5, and M6 outputs. CLKINBYPASS defaults to the master oscillator input (typically 24 MHz). SPRUH73E–October 2011–Revised May 2012 Power, Reset, and Clock Management (PRCM) Submit Documentation Feedback Copyright © 2011–2012, Texas Instruments Incorporated 655
Power, Reset, and Clock Management www.ti.com Table 8-21. Bus Interface Clocks SGX530 (MEMCLK & SYSCLK), LCDC, MPU Subsystem, L3F_CLK GEMAC Switch (Ethernet), DAP, PRU-ICSS, EMIF, TPTC, TPCC, OCMC RAM, DEBUGSS L3S_CLK USB, TSC, GPMC, MMCHS2, McASP0, McASP1 L4_PER_CLK L4_WKUP_CLK 8.1.6.6.1 Core PLL Configuration DCAN0, DCAN1 DMTIMER2, DMTIMER3, DMTIMER4, DMTIMER5, DMTIMER6, DMTIMER7 eCAP/eQEP/ePWM0, eCAP/eQEP/ePWM1, eCAP/eQEP/ePWM2, eFuse ELM, GPIO1, GPIO2, GPIO3 I2C1, I2C2, IEEE1500, LCD, Mailbox0 McASP0, McASP1 MMCHS0, MMCHS1, OCP Watchpoint, SPI0, SPI1, Spinlock UART1, UART2, UART3, UART4, UART5 ADC_TSC, Clock Manager, Control Module DMTIMER0, DMTIMER1_1MS, GPIO0 I2C0, M3UMEM, M3DMEM, SmartReflex0, SmartReflex1 UART0, WDT1 1. Switch PLL to bypass mode by setting CM_CLKMODE_DPLL_CORE.DPLL_EN to 0x4. 2. Wait for CM_IDLEST_DPLL_CORE.ST_MN_BYPASS = 1 to ensure PLL is in bypass (CM_IDLEST_DPLL_CORE.ST_DPLL_CLK should also change to 0 to denote the PLL is unlocked). 3. Configure Multiply and Divide values by setting CM_CLKSEL_DPLL_CORE.DPLL_MULT and DPLL_DIV to the desired values. 4. Configure M4, M5 and M6 dividers by setting HSDIVIDER_CLKOUT1_DIV bits in CM_DIV_M4_DPLL_CORE,CM_DIV_M5_DPLL_CORE, and CM_DIV_M6_DPLL_CORE to the desired values. 5. Switch over to lock mode by setting CM_CLKMODE_DPLL_CORE.DPLL_EN to 0x7. 6. Wait for CM_IDLEST_DPLL_CORE.ST_DPLL_CLK = 1 to ensure PLL is locked (CM_IDLEST_DPLL_CORE.ST_MN_BYPASS should also change to 0 to denote the PLL is out of bypass mode). Note: M4, M5, and M6 dividers can also be changed on-the-fly so that there is no need to put the PLL in bypass and back to lock mode. After changing CM_DIV_Mx_DPLL_CORE.DPLL_CLKOUT_DIV, check CM_DIV_Mx_DPLL_CORE.DPLL_HSDIVIDER_CLKOUT1_DIVCHACK for a toggle (a change from 0 to 1 or 1 to 0) to see if the change was acknowledged by the PLL. 8.1.6.7 Peripheral PLL Description The Per PLL provides the source for peripheral functional clocks. The Per PLL comprises an ADPLLLJ and additional dividers and muxes located in the PRCM as shown 656 Power, Reset, and Clock Management (PRCM) SPRUH73E–October 2011–Revised May 2012 Submit Documentation Feedback Copyright © 2011–2012, Texas Instruments Incorporated
Page 1 and 2: Chapter 8 SPRUH73E-October 2011-Rev
Page 3 and 4: Power, Reset, and Clock Management
Page 23: Power, Reset, and Clock Management
Page 75 and 76:
Power, Reset, and Clock Management
Page 77 and 78:
Page 79 and 80:
Page 81 and 82:
Page 83 and 84:
Page 85 and 86:
Page 87 and 88:
Page 89 and 90:
Page 91 and 92:
Page 93 and 94:
Page 95 and 96:
Page 97 and 98:
Page 99 and 100:
Page 101 and 102:
Page 103 and 104:
Page 105 and 106:
Page 107 and 108:
Page 109 and 110:
Page 111 and 112:
Page 113 and 114:
Page 115 and 116:
Page 117 and 118:
Page 119 and 120:
Page 121 and 122:
Page 123 and 124:
Page 125 and 126:
Page 127 and 128:
Page 129 and 130:
Page 131 and 132:
Page 133 and 134:
Page 135 and 136:
Page 137 and 138:
Page 139 and 140:
Page 141 and 142:
Page 143 and 144:
Page 145 and 146:
Page 147 and 148:
Page 149 and 150:
Page 151 and 152:
Page 153 and 154:
Page 155 and 156:
Page 157 and 158:
Page 159 and 160:
Page 161 and 162:
Page 163 and 164:
Page 165 and 166:
Page 167 and 168:
Page 169 and 170:
Page 171 and 172:
Page 173 and 174:
Page 175 and 176:
Page 177 and 178:
Page 179 and 180:
Page 181 and 182:
Page 183 and 184:
Page 185 and 186:
Page 187 and 188:
Page 189 and 190:
Page 191 and 192:
Page 193 and 194:
Page 195 and 196:
Page 197 and 198:
Page 199 and 200:
Page 201 and 202:
Page 203 and 204:
Page 205 and 206:
Page 207 and 208:
Page 209 and 210:
Page 211 and 212:
Page 213 and 214:
Page 215 and 216:
Page 217 and 218:
Page 219 and 220:
Page 221 and 222:
Page 223 and 224:
Page 225 and 226:
Page 227 and 228:
Page 229 and 230:
Page 231 and 232:
Page 233 and 234:
Page 235 and 236:
Page 237 and 238:
Page 239 and 240:
Page 241 and 242:
Page 243:
show all

Chapter 08 Power, Reset, and Clock Management (PRCM).pdf

You also want an ePaper? Increase the reach of your titles

Delete template?

Save as template?