Chapter 08 Power, Reset, and Clock Management (PRCM).pdf

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www.ti.com Power, Reset, and Clock Management Table 8-28. CM_PER_L4LS_CLKSTCTRL Register Field Descriptions (continued) Bit Field Type Reset Description 1-0 CLKTRCTRL R/W 2h Controls the clock state transition of the L4 SLOW clock domain in PER power domain. 0x0 = NO_SLEEP : NO_SLEEP: Sleep transition cannot be initiated. Wakeup transition may however occur. 0x1 = SW_SLEEP : SW_SLEEP: Start a software forced sleep transition on the domain. 0x2 = SW_WKUP : SW_WKUP: Start a software forced wake-up transition on the domain. 0x3 = Reserved : Reserved. SPRUH73E–October 2011–Revised May 2012 Power, Reset, and Clock Management (PRCM) Submit Documentation Feedback Copyright © 2011–2012, Texas Instruments Incorporated 681
Power, Reset, and Clock Management www.ti.com 8.1.12.1.2 CM_PER_L3S_CLKSTCTRL Register (offset = 4h) [reset = Ah] CM_PER_L3S_CLKSTCTRL is shown in Figure 8-23 and described in Table 8-29. This register enables the domain power state transition. It controls the SW supervised clock domain state transition between ON-ACTIVE and ON-INACTIVE states. It also hold one status bit per clock input of the domain. Figure 8-23. CM_PER_L3S_CLKSTCTRL Register 31 30 29 28 27 26 25 24 Reserved Reserved R-0h R-0h 23 22 21 20 19 18 17 16 Reserved R-0h 15 14 13 12 11 10 9 8 Reserved Reserved Reserved Reserved R-0h R-0h R-0h R-0h 7 6 5 4 3 2 1 0 Reserved Reserved CLKACTIVITY_L3S_ Reserved CLKTRCTRL GCLK R-0h R-0h R-1h R-0h R/W-2h LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset Table 8-29. CM_PER_L3S_CLKSTCTRL Register Field Descriptions Bit Field Type Reset Description 31-26 Reserved R 0h 25-11 Reserved R 0h 10 Reserved R 0h 9 Reserved R 0h 8 Reserved R 0h 7-5 Reserved R 0h 4 Reserved R 0h 3 CLKACTIVITY_L3S_GCL R 1h This field indicates the state of the L3S_GCLK clock in the domain. K 0x0 = Inact 0x1 = Act 2 Reserved R 0h 1-0 CLKTRCTRL R/W 2h Controls the clock state transition of the L3 Slow clock domain. 0x0 = NO_SLEEP : NO_SLEEP: Sleep transition cannot be initiated. Wakeup transition may however occur. 0x1 = SW_SLEEP : SW_SLEEP: Start a software forced sleep transition on the domain. 0x2 = SW_WKUP : SW_WKUP: Start a software forced wake-up transition on the domain. 0x3 = Reserved : Reserved. 682 Power, Reset, and Clock Management (PRCM) SPRUH73E–October 2011–Revised May 2012 Submit Documentation Feedback Copyright © 2011–2012, Texas Instruments Incorporated
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Chapter 08 Power, Reset, and Clock Management (PRCM).pdf

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