Chapter 08 Power, Reset, and Clock Management (PRCM).pdf

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www.ti.com Power, Reset, and Clock Management Table 8-26. Power Domain of Various Modules (continued) Power Supply Power Domain Modules OR Supply Destinations (sinks) Toplevel: Pinmux gates/logic, oscillator wake logic DDR PHY (DIDs) WKUP_DFTSS Debugs Digital section (VDD) of CORE PLL, PER PLL, Display PLL and DDR PLL Emulation sections of MPU VDD of all IOs including crystal oscillators RC Oscillator Infrastructure: L3 L4_PER, L4_Fast, L4_FW VDD_CORE EMIF4 EDMA GPMC OCMC controller L3 / L4_PER / L4_Fast / L4_FW Peripherals PRU-ICSS LCD controller Ethernet Switch USB Controller GPMC MMC0..2 DMTIMER2..7 PD_PER Uart1..5 SPI0, 1 I2C1, 2 DCAN0, 1 McASP0, 1 ePWM0..2 eCAP0..2 eQeP0,1 GPIO1..3 ELM Mailbox0, Spinlock OCP_WP Others: USB2PHYCORE (VDD/digital section) USB2PHYCM (VDD/digital section) PD_GFX SGX530 PD_MPU CPU, L1, L2 of MPU VDD_MPU Interrupt controller of MPU Subsystem PD_WKUP Digital Portion (VDD) of MPU PLL 1. RTC VDD_RTC PD_RTC VDD for 32 768 Hz Crystal Osc VDD for IO for the alarm pin SPRUH73E–October 2011–Revised May 2012 Power, Reset, and Clock Management (PRCM) Submit Documentation Feedback Copyright © 2011–2012, Texas Instruments Incorporated 675
Power, Reset, and Clock Management www.ti.com 8.1.11.1 Power Domain Power Down Sequence The following sequence of steps happen during the power down of a power domain All IPs (belonging to a power domain) with STANDBY interface will assert STANDBY. STANDBY assertion should get triggered by IP based on its activity on OCP initiator port. IP should assert STANDBY whenever initiator port is IDLE. Some of the IPs may not have this feature and they will require SW write to standby-mode register to get STANDBY assertion from IP. 1. SW will request all modules in given power domain to go to disable state by programming module control register inside PRCM. 2. PRCM will start and wait for completion of power management handshake with IPs (IdleReq/IdleAck). 3. PRCM will gate-off all the clocks to the power domain. 4. SW will request all clock domains in given power domain to go to “force sleep” mode by programming functional clock domain register in PRCM. Note that PRCM has already gated-off clocks and this register programming may look redundant. 5. SW will request PRCM to take this power domain to OFF state by programming PWRSTCTRL register. Note that this step can be skipped if PWRSTCTRL is permanently programmed to OFF state. When this is done, functional clock domain register decides when power domain will be taken to OFF state. Only reason not to have OFF state in PWRSTCTRL is to take power domain to just clock gate state without power gating. 6. PSCON specific to this power domain will assert isolation enable for the domain. 7. PRCM will assert warm and cold reset to the power domain. 8. PSCON will assert control signals to switch-off power using on-die switches. 9. On-die switches will send acknowledge back to PSCON. 8.1.11.2 Power Domain Power-Up Sequence The following sequence of steps occurs during power-up of a power domain. This sequence is not relevant to always-on domain as this domain will never go to OFF state as long as the device is powered. This sequence will be repeated each time a domain is taken to ON state from OFF (including first time power-up). Note that some of the details are intentionally taken out here to simplify things. There can be multiple reasons to start power-up sequence for a domain. For example it can be due to an interrupt from one of the IPs which is powered-up. 1. SW will request required clock domains inside this power domain to go to force wake-up state by programming functional clock domain register. 2. PRCM will enable clocks to the required clock domains. 3. PSCON specific to this power domain will assert control signal to un-gate the power. 4. Once power is un-gated, on die switches will send acknowledge back to PSCON. 5. PRCM will de-assert cold and warm reset to the power domain. 6. PRCM will turn-off isolation cells. 7. SW will request PRCM to enable required module in the power domain by programming module control register. 8. PRCM will initiate and wait for completion of PM protocol to enable the modules (IdleReq/IdleAck). 676 Power, Reset, and Clock Management (PRCM) SPRUH73E–October 2011–Revised May 2012 Submit Documentation Feedback Copyright © 2011–2012, Texas Instruments Incorporated
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