Chapter 08 Power, Reset, and Clock Management (PRCM).pdf

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www.ti.com Power, Reset, and Clock Management Figure 8-6. System Level View of Power Management of Cortex A8 MPU and Cortex M3 INTR2 WKUP PD_GFX PD_MPU (Cortex-A8) MSG3 16KB unified RAM 8KB DRAM Cortex-M3 subsystem TXEV RXEV Legend: PD_PER MBX INTR3 Cortex- M3 MSG1 INTR1 System power clock manager Interrupt Alternate Interrupt/Event s/w message Alternate s/w message Data flow Bus Interconnect Bus MSG3 Table 8-14. M3 Interrupts 1–3 IP/Peripherals Power connect/ disconnect Power Idle PRCM Control Interrupt Name Interrupt Number in M3 Explanation INTR1 (PRCM_M3_IRQ1) 16 Power Idle Generated by PRCM when MPU power domain is clock gated. INTR2 (PRCM_M3_IRQ2) 34 Generated by wakeup events SPRUH73E–October 2011–Revised May 2012 Power, Reset, and Clock Management (PRCM) Submit Documentation Feedback Copyright © 2011–2012, Texas Instruments Incorporated 645
Power, Reset, and Clock Management www.ti.com Table 8-14. M3 Interrupts 1–3 (continued) Interrupt Name Interrupt Number in M3 Explanation INTR3 (MBINT0) 31 Mailbox interrupt to M3 8.1.4.6.1 Periodic Idling of Cortex A8 MPU To implement Cortex A8 MPU periodic ON/OFF in the use case, the control flow could be implemented according to the following steps: 1. Cortex A8 MPU executes WFI instruction 2. Any peripheral interrupt in any of the next steps will trigger a wake interrupt to CortexM3 via MPU Subsystem’s WKUP signal (INTR2 shown on the diagram). Cortex M3 powers down the MPU(PD_MPU) 3. On receiving an interrupt Cortex M3 switches ON the MPU power domain by turning on PD_MPU 4. Cortex M3 goes into idle mode using WFI instruction 8.1.4.6.2 Sleep Sequencing This section gives the system level guidelines for sleep sequencing. The guidelines can serve as an example for implementing the sleep mode sequencing. The user can opt to implement a sequence with certain steps interchanged between the MPU and Cortex M3 processor. 1. Application saves context of peripherals to memories supporting retention and DDR – this step is only required for Deepsleep0. 2. MPU OCMC_RAM remains in retention 3. Unused power domains are turned OFF - program clock/power domains PWRSTCTRL, save contexts etc 4. Software populates L3_OCMC_RAM for wakeup restoration viz Save EMIF settings, public restoration pointers, etc. 5. Execute WFI from SRAM 6. Any peripheral interrupt will trigger a wake interrupt to CortexM3 via Cortex A8 MPU’s WKUP signal (INTR2 shown on the diagram). 7. After MPU power domain is clock gated PRCM will provide an interrupt to CortexM3 (using INTR1 shown in the block diagram) 8. CortexM3 starts execution as follows: • CortexM3 configures PLL / HSDIVIDER power down States (bypass modes). During Idle bypass mode (low power mode) the PLL / HSDIVIDER goes into bypass and provides the clock outputs directly from the oscillator clock. • CortexM3 disables IP/Peripheral/Interconnects based on MSG1/MSG2/MSG3 sconnect/disconnect/Idle protocol kicks off and completes • PRCM turns OFF power domains based on MSG1/MSG2/MSG3 Only applicable for DeepSleep0 & DeepSleep1. • CortexM3 lowers the PMIC voltage to OPP50 voltage • CortexM3 configures I/O PADs for lowest power as dictated by CortexA8 using MSG2/MSG3 • CortexM3 goes into WFI 9. Hardware oscillator control circuit disables the oscillator once CortexM3 goes into WFI 8.1.4.6.3 Wakeup Sequencing This section gives the guidelines for Wakeup sequencing. 1. One of the wakeup event triggers (which was configured during the sleep sequencing) will initiate a wakeup sequence 2. The wake up event will switch on the oscillator (if it was configured to go OFF during sleep) 646 Power, Reset, and Clock Management (PRCM) SPRUH73E–October 2011–Revised May 2012 Submit Documentation Feedback Copyright © 2011–2012, Texas Instruments Incorporated
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