Chapter 08 Power, Reset, and Clock Management (PRCM).pdf

www.ti.com Power, Reset, and Clock Management
Note: M2 divider can also be changed on-the-fly (ie., there is no need to put the PLL in bypass and back
to lock mode). After changing CM_DIV_M2_DPLL_DISP.DPLL_CLKOUT_DIV, check
CM_DIV_M2_DPLL_DISP.DPLL_CLKOUT_DIVCHACK for a toggle (a change from 0 to 1 or 1 to 0) to
see if the change was acknowledged by the PLL.
8.1.6.10 DDR PLL Description
The DDR PLL provides the clocks required by the DDR macros and the EMIF and is independent from the
other peripheral and infrastructure clocks. The PLL is clocked from the Master Oscillator. The ADPLLS M2
divider determines the output clock frequency which is connected directly to the DDR Macros. The clock is
also routed through the PRCM where a fixed /2 divider is used to create the M_CLK used by the EMIF as
shown in Figure 8-13.
Master
Osc
(CLK_M_OSC)
ALT_CLK1
ALT_CLK2
TEST.CDR (via P1500)
CORE_CLKOUTM6
PER_CLKOUTM2
CONTROL.PLL_CLKINPULOW_CTRL.DDR_
PLL_CLKINPULOW_SEL (Reset default = 0)
PRCM.CM_CLKSEL_DPLL_DDR.
DPLL_BYP_CLKSEL (Reset default = 0)
Figure 8-13. DDR PLL Structure
0
1
2
0
1
DDR PLL
(ADPLLS)
CLKINP
CLKOUT
CLKOUTHIF
CLKDCOLDO
CLKINPULOW
ULOWCLKEN
0: CLKINP
1: CLKINPULOW
ULOWPRIORITY
For OPP information, see the device-specific data manual.
CLKOUTx2
PRCM
/2
IDID IDID
IDID
macros
EMIF M_CLK
Example frequency for DDR clock, say 266 MHz, the ADPLLS is configured (PLL locked at 532 MHz and
M2 Divider =1) so as to expect CLKOUT = 266 MHz.
The ULOWCLKEN input from a programmable PRCM register selects whether CLKINP or CLKINPULOW
is the bypass clock source. This is a glitch free switch. When CLKINP is selected it is sourced through the
ADPLLS 1/(N2+1) divider. The PRCM register defaults to 0 on power-up to select the CLKINP source.
The CLKINPULOW input may be sourced from the CORE_CLKOUTM6 from the Core PLL, or
PER_CLKOUTM2 from the Per PLL. These PLL output clocks can be used as alternate clock sources in
low power active use cases for the DDR clocks when PLL is in bypass mode
8.1.6.10.1 Configuring the DDR PLL
The following steps detail how to configure the DDR PLL.
1. Switch PLL to bypass mode by setting CM_CLKMODE_DPLL_DDR.DPLL_EN to 0x4.
2. Wait for CM_IDLEST_DPLL_DDR.ST_MN_BYPASS = 1 to ensure PLL is in bypass
(CM_IDLEST_DPLL_DDR.ST_DPLL_CLK should also change to 0 to denote the PLL is unlocked).
3. Configure Multiply and Divide values by setting CM_CLKSEL_DPLL_DDR.DPLL_MULT and
DPLL_DIV to the desired values.
4. Configure M2 divider by setting CM_DIV_M2_DPLL_DDR.DPLL_CLKOUT_DIV to the desired value.
5. Switch over to lock mode by setting CM_CLKMODE_DPLL_DDR.DPLL_EN to 0x7.
6. Wait for CM_IDLEST_DPLL_DDR.ST_DPLL_CLK = 1 to ensure PLL is locked
(CM_IDLEST_DPLL_DDR.ST_MN_BYPASS should also change to 0 to denote the PLL is out of
bypass mode).
SPRUH73E–October 2011–Revised May 2012 Power, Reset, and Clock Management (PRCM)
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