FPGA based Hardware Accleration for Elliptic Curve Cryptography ...

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2.2. FINITE FIELD ARITHMETIC 12
Hardware implementations of the polynomial reduction can especially benefit from hard-coded prime
polynomials with low Hamming weight such as trinomials or pentanomials. Such polynomials are typical
for cryptographic and exist for all interesting EC parameter sets.
Given a prime trinomial
6 5 )‡59ãä)Oc the reduction process can be performed efficiently by using the
identities:
Ü 5 ã )²c ͉Ï4Ð 5
ª Y Ü 5 㪠Y ),5 Í7Ï4Ð 5
.
This leads to
5 3 Ü 5 㪠) binary XOR operations for one polynomial reduction. Reduction of
pentanomials can be performed similar leading to some additional XOR operations. The particular terms
(1...5) of the final equation are structured according to Fig. 2.3 in order to perform the reduction. With
respect to the implementation a single( -bit register is sufficient to store the resulting bit string.
åYºæ
å3 æ
å8 æ
å$Aæ
åèç æ
¢ £h¤ ¥
¢ £¤ ¥
¢ £¤ ¥
¢ £h¤ ¥
¢ £¤ ¥
) =­ Y ­ ã
) ã­ Y
) ã­ Y
) =­ Y
±ÈÇÉ® Ò ±K5 ±
±ÈÇÉ® Ò ±ª 5 㪠±
±–ÇÉ® Ò 3 =­ 㪠±5 㪠±
±ÈÇÉ® Ò 3 P­ 㪠±5 ±
±ÈÇÉ® Ò ª ±K5 ±
n−1 0
(1)
2n−1
2n−b−1 n 2n−1 2n−b
(2) (4)
2n−1
(5)
2n−b
(3)
Result Register (n bit)
Figure 2.3: Structure of the polynomial reduction
n