08.03.2014 Views

FPGA based Hardware Accleration for Elliptic Curve Cryptography ...

FPGA based Hardware Accleration for Elliptic Curve Cryptography ...

FPGA based Hardware Accleration for Elliptic Curve Cryptography ...

SHOW MORE
SHOW LESS

Create successful ePaper yourself

Turn your PDF publications into a flip-book with our unique Google optimized e-Paper software.

6 v | }<br />

v Yg5 ¦î 3 ¾ v ®SaP| Yg5 î 3 ¾ | ®S 6<br />

v Y | Yg5 ¾ v Y | ®[5 î 3 ¾ v ® | Yg5 ¦î 3 ¾ v ® | ®<br />

6<br />

6 v Y | Y<br />

ú<br />

ü v Y | Y<br />

ü v ® | ®<br />

Y 0ó6 v Y | Y l<br />

3 0ó6 v Ya¾ v ®Sb=| Ya¾ | ®S l<br />

v Y | ®Ú¾ v ® | YD¾ v Y | Yb¾ v ® | ® 6<br />

l<br />

8<br />

8<br />

8<br />

2.3. SEQUENTIAL MULTIPLICATION SCHEMES 15<br />

Fig. 2.4a illustrates the schoolbook multiplication <strong>for</strong> 6°ñ<br />

. The gray boxes represent the results of<br />

the degree+ respective polynomial multiplications, which are denoted next to the boxes. The horizontal<br />

position of a box indicates its ò 5 0ó6 59ô offset . The ordering of the partial products by<br />

¯<br />

decreasing<br />

allows <strong>for</strong> the accumulation of the final result in a shift register and the application of an interleaved<br />

reduction scheme as detailed in Sec. 3.4.6.<br />

5 ±<br />

with ò<br />

2.3.2 Polynomial Karatsuba Multiplication<br />

In 1963 A. Karatsuba and Y. Ofman developed an algorithm of complexity õ7K(Úöø÷Cù 8 that computes the<br />

product of two( -bit integers [17].<br />

Like the Schoolbook Multiplication, this algorithm divides the operands into two equal parts. Adopting<br />

the arithmetical operations tohÁ5. leads to<br />

¢ £h¤ ¥<br />

¢ £¤ ¥<br />

¢ £h¤ ¥<br />

¢ £h¤ ¥<br />

¢ £h¤ ¥<br />

úû 5 ¾ÆÁ–v Ya¾ v ®Sh| Ya¾ | ®S<br />

úBý ÂÈ5 î 3 ¾ v ® | ®<br />

úû<br />

úBý<br />

6 l Y 5 ¾²Ál 3 ü l Y ü l<br />

8 ÂÈ5 ¦î 3 ¾ l<br />

8<br />

(2.11)<br />

6 l Y 5 ¾²Ál Y ¾ l 3 ¾ l<br />

8<br />

given by<br />

8 ÂÈ5 ¦î 3 ¾ l<br />

withl<br />

YZ@ l 3 andl<br />

v ® | ®k\ 0ó6<br />

Thus, the final product can be computed by 3 multiplications and 2 additions degree(b†¦ of polynomials<br />

and 4 additions degree( of polynomials as illustrated in Fig. 2.5. Again, since the addition can be computed<br />

combinationally in the same cycle as a partial multiplication, the complete multiplication takes 3 cycles<br />

only. By splitting the into<br />

6 ±<br />

factors segments any¯ EN©<br />

(<strong>for</strong> ), the product can be withþ=öø÷Cù ¦<br />

computed<br />

multiplications by a recursive application of this scheme.<br />

Due to the need to store intermediate results and to maintain a stack, recursive algorithms are not appropriate<br />

<strong>for</strong> hardware implementations. The recursion has thus to be unrolled. Fig. 2.4b shows the resulting<br />

degree+<br />

multiplication scheme <strong>for</strong> an unrolled recursion of the Karatsuba with<br />

6Šñ<br />

multiplication . Each pattern<br />

in Fig. 2.4b, which is additionally surrounded by a gray box, can be composed from one partial multiplication.<br />

The labels at the right side of the boxes determine the indices of the segments, whose sums have been<br />

multiplied. E.g., the label "13" denotes the termv<br />

Ya¾ v<br />

8 .<br />

6 v Y | ®Ú¾ v ® | YD¾ l Ya¾ l<br />

8 b=| Yb¾ |

Hooray! Your file is uploaded and ready to be published.

Saved successfully!

Ooh no, something went wrong!