FPGA based Hardware Accleration for Elliptic Curve Cryptography ...

3.4. FINITE FIELD ARITHMETIC 22
3.4.3 Input Stage
The input stage provides two accumulation registers, i.e., one for each operand of the combinational multiplier.
Besides parallel load functionality these registers must be capable of adding one new segment to its
current value, as stated in Sec. 2.3.3. According to part (c) of Fig. 3.2 the following logic gatecounts are
required to build up the input stage for a& #" ¦ based on a+ -bit combinational multiplier:
6 k+ "!ƒe 3$#YBK+F@A. 6 k+&% v
€ 3 K+ˆ 6dñ + e('U 3 K+ˆ 6 k+
npn*K+ˆ
remark:"!ƒe 3$#Y Please components with constant zero inputs have been tov
€ 3 optimized gates.
3.4.4 Combinational Multiplier (CKM)
As stated before in Sec. 2.2.1 and shown in Fig. 3.3a the product of two one bit polynomials is computed by
a single AND operation.
a a b
3 2 3
a a b 1 0 1
a 0 b 0
c 2
c 0
c 1
c 0
c c c c c
6 5 4 3
c c
2 1 0
b 0
a 1
a 0
b 1
b 0
CKM2
CKM2
CKM1
CKM1
CKM2
CKM1
b
2
a) 1−bit CKM
b) 2−bit CKM
c) 4−bit CKM
Figure 3.3: Recursive construction process for polynomial Karatsuba multipliers
Using Karatsuba’s divide and conquer multiplication algorithm, a multiplication of two( -bit polynomials
can be computed with three(b†¦ -bit multiplications and some additions (which are XOR’s in our case) to
determine interim results and accumulate the final result. This leads immediately to a recursive construction
process, which builds combinational Karatsuba multipliers (CKM) of width(
6 ô for arbitrary+
E