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FPGA based Hardware Accleration for Elliptic Curve Cryptography ...

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2.3. SEQUENTIAL MULTIPLICATION SCHEMES 13<br />

Due to the complexity of a reduction step, in the following this work diverts the arithmetic operations in<br />

into two successive parts. The arithmetical operation:hÁ5. corresponding to that in- and<br />

with a degreeÕ<br />

( and the subsequent reduction step.<br />

2.3 Sequential Multiplication Schemes<br />

In order to achieve a reasonable level of security <strong>for</strong> an EC cryptosystem, the extension degree ( of the<br />

underlying finite field has to be in the hundreds. Due to chip area limitations an application of<br />

combinational multipliers of full bit width ( is usually not feasible. Instead, a sequential multiplication<br />

scheme, which is <strong>based</strong> on a reasonable sized purely combinational multiplier unit, has to be utilized. In<br />

Sec. 3.4.4 the architecture of such a combinationalhÁ5. multiplier is presented, which is scalable and<br />

highly efficient in terms of required logic resources.<br />

In the remainder of this section it is assumed that a reasonable sized combinational multiplier, which<br />

computes the unreduced product of two degree +êé ( polynomials, is part of the design. Some wellknown<br />

methods <strong>for</strong> sequential multiplication are introduced first. Then, in Sec. 2.3.3, the Multi-Segment<br />

Karatsuba multiplication scheme is detailed and compared to classical approaches.<br />

2.3.1 Schoolbook Multiplication<br />

Given two polynomialsv<br />

@ |ëE -hÁ5ÃÂ of degree( and a combinational multiplier of size+<br />

6ëì(b†¦kí ,<br />

the product} 6 v |<br />

can be computed as follows: Firstv<br />

and|<br />

are split each into two segments of equal<br />

size.<br />

Then the product can be computed as<br />

6 v YC5 î 3 ¾ v ® v<br />

6 | YC5 î 3 ¾ | ® |<br />

6 v | }<br />

v Yg5 î 3 ¾ v ®ZaP| Yg5 î 3 ¾ | ® 6<br />

v YÚ | YC5 ¾Æv YÚ | ®Ú¾ v ®j | Y[º5 î 3 ¾ v ®j | ®k\ (2.10)<br />

6<br />

Please note that in the context of hardware implementations the5<br />

±<br />

factors correspond to position offsets,<br />

which can simply be implemented by appropriate wiring.<br />

Generally, the polynomials can be split into an arbitrary number of segments<br />

E”© ª<br />

. It is selected such<br />

that the resulting segments are small enough to be multiplied on the combinational multiplier (+ ³ (b†¦ ).<br />

The number of necessary multiplications is given by<br />

3<br />

. Since the additions can be computed combinationally<br />

in the same cycle, the cycle count <strong>for</strong> a complete multiplication is also given by<br />

3<br />

.<br />

A variation of the schoolbook method splits each of the two polynomialsv<br />

and|<br />

into different numbers<br />

of segments (=ïÚ@A=ð .) Of course, in this case an appropriate asymmetric combinational multiplier is necessary<br />

2 . The number of required multiplications is given here by.ïˆBPð . In the extreme case of4ï 6 ( and<br />

=ð 6 c this scheme is called bit serial multiplication.<br />

2 This topic is extensively treated in [16].

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