FPGA based Hardware Accleration for Elliptic Curve Cryptography ...

3.2. REGISTER FILE 20
3.2 Register File
Part (b) of Fig. 3.1 covers the Register File. It provides c registers of( -bit width. These registers are
implemented by using FPGA internal Lookup Tables (LUT) and provide a dual ported interface allowing
concurrent read and write access to the data. Currently ¤ registers are used as internal temporary registers
for the EC algorithms and can therefore not be accessed by the user. The remaining ¤ register are left for
field parameters, input operands and results. By modifying the EC level algorithms the requirements for
internal temporary registers might change.
3.3 EC Arithmetic
The EC Arithmetic, highlighted as part (c) in Fig. 3.1, implements the algorithm and the underlying
EC operations EC-Add and EC-Double. It also implements the FF-Inversion that is intrinsically not an
EC level operation. But since it is realized by the control flow oriented algorithm and composed of basic
arithmetic operations in just like the EC level operations, FF-Inversion has been implemented here
(see Alg. 4).
Beside of the controller the module contains a single shift register of( -bit size. This register is needed to
scan bit-wise as required by Eqn. 3.
The controller is implemented by several Finite State Machines (FSM) in a hierarchical order. Each FSM
controls one arithmetical operation, i.e., the algorithm, the EC-Add and the EC-Double operation.
The hierarchical ordering of FSMs is considered to be the best tradeoff between speed and flexibility.
Leaving the controller logic inside the software would provide more flexibility for changing EC level algorithms
at the cost that pipelining delays and parallel operation of different modules becomes much more
complicated (or might even be impossible). Furthermore the overhead and the delay for communication over
the PCI interface makes this solution impracticable. The other way would be a single controller to prevent
possible delays emerging from communication between the different FSMs. The great disadvantage of this
approach is, that due to the unmanageable side-effects inside such an FSM, modifications of one algorithm
(e.g. the EC algorithm) would lead to a rewrite of the whole controller and not just the EC controller.
3.4 Finite Field Arithmetic
The finite field arithmetic that is denoted as part (d) in Fig. 3.1 is the most expensive part of the EC coprocessor.
Due to the complexity it is split into separate modules that provide the functionality of the operations
described in Sec. 2.2. A general overview of the datapath is given in Fig. 3.2. The particular parts depicted
in this picture are described subsequently and the corresponding gate counts are summarized in Tab. 3.2.
3.4.1 Addition
According to Eqn. 2.4 the addition inhÁ5ÃÂ is a just an( -bit wide XOR with no need for a subsequent
reduction step. A complete addition can be performed in one cycle. So part (a) of Fig. 3.2 takes( XORgates
of logic resources for it’s implementation. Please note, that the input registers are part of the Register
File and the result register is used by all finite field operations together, because of which it’s FlipFlops are
counted only once in part (f).