FPGA based Hardware Accleration for Elliptic Curve Cryptography ...

List of Figures
c)! #"%$ d)& #"'$
2.1 Example of an EC visualizing the point addition . . . . . . . . . . . . . . . . . . . . . . . . 5
2.2 EC arithmetic hierarchy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.3 Structure of the polynomial reduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.4 Sequential Multiplication Schemes: a) Schoolbook method; b) unrolled Karatsuba for 2
recursion steps; before reordering of the subterms; after reordering of
the subterms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.5 Polynomial Karatsuba multiplication scheme . . . . . . . . . . . . . . . . . . . . . . . . . 16
of(*),+
3.1 Generic Datapath of the EC coprocessor . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.2 Generic Datapath of the Finite Field Arithmetic . . . . . . . . . . . . . . . . . . . . . . . . 21
3.3 Recursive construction process for polynomial Karatsuba multipliers . . . . . . . . . . . . . 22
3.4 Combinational Karatsuba Multiplier gate count . . . . . . . . . . . . . . . . . . . . . . . . 23
3.5 Structure of the polynomial reduction bit . . . . . . . . . . . . . . . . . . . . . . 24
4.1 microEnable PCI card . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
4.2 Atmel AT94K40 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28