FPGA based Hardware Accleration for Elliptic Curve Cryptography ...

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3.5. VHDL-CODE GENERATOR 25
Table 3.2: Datapath gatecount
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Datapath
Part (a)
Part (b)
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(c)
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(d)
Part K E K EFK
(e)
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(f)
3.5 VHDL-Code Generator
In this section the VHDL-Code Generator is presented. Though VHDL offers several possibilities to generalize
code statements this opportunities are not sufficient to implement a design as scalable as required
in this application. E.g., it would not be possible to generalize the reduction logic due to the variable
prime polynomials. To provide the wanted scalability a generator based approach proposed in [10] has been
adopted where the VHDL code is generated by a C program. The generator consists of one top-level file
calculating some internal variables out of the user input parameters, opening the files into which the VHDL
code is written and calling the appropriate subroutines. Each subroutine is implemented in a separate file
and generates the VHDL description (entity and architecture) for one particular hardware module.
The generator takes several parameters that are implemented as commandline parameters. Currently these
parameters are:
Key Size [Bits]:
r
The Key Size specifies the overall bit width of the coprocessor. A given constraint is that this number
must be smaller than the CKM size multiplied by the number of segments.
Combinational Karatsuba Multiplier (CKM) size [Bits]:
r
The CKM size specifies the width of the combinational part of the multiplier. Since the size of the
CKM is exponentially dependent on it’s bit width, this value is essential determining the resource
consumption of the complete ECC coprocessor.
Bit Position of the middle bit in the prime trinomial [Int]:
r
The bit position of the middle bit in the prime trinomial is needed for reduction component. The
position of the highest bit is already specified by the key size and and the lowest bit is fixed be5
®
to .
The current generator is only capable of trinomials. Supporting pentanomials would be possible by
slight modifications of the generator.
Number of Segments [Int]:
r
The type of MSK is specified by the number of segments. Currently the generator is limited from
three to seven segments which are regarded as the most interesting ones. Additional support of new
MSK sizes can be applied by adding a new subroutine to the ’generate_ff_controller’ routine in the
generator program. Outside the controller the number of segments does not have any influences to the
design.
Card Type [1|2]:
r
The card type specifies which hardware dependent top level module should be instantiated. ’1’ is