FPGA based Hardware Accleration for Elliptic Curve Cryptography ...

1.3. GOALS OF THIS STUDY 3
specific and synthesizable VHDL descriptions from a superior, generic coprocessor-model has also been
adopted from this previous design.
1.3 Goals of this Study
The main goal of this work is the design and the implementation of a arithmetic processor kernel
which can be embedded into the previously described EC coprocessor design. After some research on
existing algorithms and implementations it was decided that the main work should concentrate on the finite
field arithmetic while the EC level algorithms should be adopted from the literature. The main reason for this
decision was the fact, that an efficient hardware architecture has a much greater influence on the efficiency
of the data flow dominated finite field algorithms than on the control flow oriented EC level algorithms.
The final design should be widely scalable in terms of different types of resource usage. To provide this
scalability and flexibility a generator program should be used to produce the VHDL hardware models, out
of which the FPGA programming bitstream is synthesized subsequently. While it was clear that the most
important parameter for scalability will be the bitwidth of the design, the complete parameter set and the
resulting degree of flexibility caused by the generator approach was specified during the implementation
progress.
A minor goal has been the compatibility to existing modules. The interface of the new developed design
should correspond to that of the existing ONB implementation. Using this goal it was possible to reuse the
already optimized EC Controller from the ONB implementation without modifications.
A new family of attacks against cryptographic hardware implementations is currently gaining much importance.
These so called Side-Channel-Attacks use additional information the hardware provides beside the
cryptographic functions to extract knowledge of the secret key. Examples for this additional information are
the runtime of an operation that might depend on the secret key or the power consumption of a chip during
the computation. Though it was not a main goal of this work to provide resistance against such attacks, the
problem should be reminded during implementation. Where possible, simple countermeasures should be
implemented.
To evaluate the functionality of the hardware implementation, the results should be compared against
results of a pure software implementation. To provide a framework for this evaluation process, the existing
C software implementation has been extended to support- elements in polynomial representation.
1.4 Content of this work
The mathematical background of elliptic curves and finite fields is introduced in the following chapter.
Furthermore, the multi-segment Karatsuba multiplication scheme is described in detail. Chap. 3 focuses on
the architecture and the implementation of the proposed ECC coprocessor. Special attention is given to the
arithmetic processor kernel. Implementation results and some performance numbers are given in
Chap. 4. Finally, Chap. 5 summarizes the conclusions and gives an outlook on work that might follow.