Automating Manufacturing Systems - Process Control and ...

plc timers - 9.4
Figure 9.3 A Timing Diagram for the Ladder Logic in Figure 9.2
The timing diagram shown in Figure 9.3 has more details than are normal in a timing
diagram as shown in Figure 9.4. The brief pulse would not normally be wanted, and
would be designed out of a system either by extending the length of the pulse, or decreasing
the scan time. An ideal system would run so fast that aliasing would not be possible.
A
B
C
D
Figure 9.4
A Typical Timing Diagram
A more elaborate example of latches is shown in Figure 9.5. In this example the
addresses are for an Allen-Bradley Micrologix controller. The inputs begin with I/, followed
by an input number. The outputs begin with O/, followed by an output number.