Power Management Design Guide for AlteraÂ® FPGAs and CPLDs ...

Power Management Design Guide for 

Altera ® FPGAs and CPLDs 

Fall 2005 

Altera devices covered: 

Stratix ® II FPGA family 

Stratix ® FPGA family 

Cyclone FPGA family 

MAX ® II CPLD family 

Also features National’s FPGA solutions for: 

• Communications interface, including LVDS 

• High-speed data conversion 

• High-speed, low-power analog signal conditioning 

www.national.com/see/alterafpga 

N a t i o n a l 

Semiconductor 

The Sight & Sound of Information

Featured power products 

LM5070 Power-over-Ethernet single-chip solution 

• Fully compliant with IEEE 802.3af PoE standards 

• Delivers up to 14W of power from regular 

CAT-5 Ethernet cable 

• Powers all Altera Cyclone and most Stratix and 

Stratix II FPGA designs without the need for wall 

adapters, batteries or any external power supply 

• Industrial temperature range 

• Evaluation boards and reference designs available 

• Available in TSSOP-16 and tiny, thermally 

enhanced LLP-16 packaging 

LM5070 Power-over-Ethernet powered device system 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

LM3670/71 600 mA SOT-23 synchronous buck regulators 

• Requires only 3 external components 

• High switching frequency, ceramic capacitors 

and SOT23-5 package enables an extremely 

small total solution 

• 600 mA, 2 MHz (LM3671) and 

350 mA, 1 MHz (LM3670) versions available 

• Can achieve 95% efficiency with just a 2.2 µH 

small inductor 

• Automatic PWM-PFM mode switching enables 

longer battery life and extended stand-by times 

• Fixed output voltage and adjustable versions 

available 

• Industrial temperature range 

• Ideal for CPLD and low-power FPGA supplies 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

LM3671 Simple block diagram 

 

 

 

 

 

 

 

LM3671 Efficiency vs. load current 

 

 

 

 

 

 

 

ii

Contents 

Featured power products for FPGAs & CPLDs 

LM5070 Power-over-Ethernet single-chip solution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ii 

LM3670/71 600 mA SOT-23 synchronous buck regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ii 

LM2743 Low-voltage synchronous buck controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 

LM2647 Dual synchronous buck controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 

LM2798, LM3352, LM2770 Inductorless switching regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 

LP385x/7x High-performance CMOS LDOs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 

How to use this guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 

Selecting the best power architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 

National power solutions for Stratix II FPGAs 

Stratix II FPGAs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 

Stratix II power requirements summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 

National power solutions for Stratix II FPGAs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 

National power solutions for Stratix FPGAs 

Stratix FPGAs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 

Stratix power requirements summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 

National power solutions for Stratix FPGAs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 

National power solutions for Cyclone FPGAs 

Cyclone FPGAs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 

Cyclone power requirements summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 

National power solutions for Cyclone FPGAs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 

National power solutions for MAX II CPLDs 

MAX II CPLDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 

National power solutions for MAX II CPLDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-11 

MAX II power requirements summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 

Design considerations for powering FPGAs & CPLDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12-13 

Reference designs for Altera FPGAs & CPLDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14-19 

Other technologies for FPGA/CPLD-based designs 

DDR memory solutions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 

Discrete LVDS buffers and transceivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 

High-speed data conversion ICs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 

High-speed, low-power amplifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 

Product summary 

Recommended V CCINT and V CCIO regulators summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 

Select voltage supervisors/power-on-reset ICs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 

Application notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 

Design tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 

Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Back 

For comments or feedback on this guide please email: 

FPGA.Power.Tools@nsc.com 

1

How to use this guide 

Introduction 

National Semiconductor — working in close collaboration 

with Altera — has developed this comprehensive design 

guide for design engineers who are utilizing Altera’s latest 

FPGAs and CPLDs, to help them easily select and implement 

the best power management solutions for their designs. 

This design guide presents National’s power supply solutions 

down to specific part numbers with multiple reference 

designs illustrating how these power management ICs 

are used in actual applications. This guide recommends 

the optimal National products for select Altera devices 

based on the device’s specified power consumption in 

specific applications. The reference designs were created by 

National and verified by Altera, combining the experience 

and knowledge of both companies to ensure that the 

highest-performing, most-reliable power solutions are 

being offered for the latest, most-powerful Altera devices. 

Additional information is available on National’s website, 

including bills of material and test data for the reference 

designs, along with detailed information on other National 

solutions for Altera FPGAs, from LVDS transceivers 

to high-speed ADC and integrated Bluetooth ® wireless 

modules. For more information, visit: 


How to use this guide 

This design guide is organized into two major sections: 

selection guide tables and reference design schematics. The 

use of this guide is a simple two-step process. 

1. In the selection guide, find the Altera FPGA or 

CPLD to be used in the design. Review the power 

consumption data for the device and select a National 

regulator for powering V CCINT and V CCIO . 

2. Go to the Reference Design section to find complete 

Altera FPGA-based power supplies using the 

recommended National product ID. 

This design guide also provides information on additional 

National ICs for FPGAs, from core power management 

(including DDR and DDR-II memory regulators and active 

termination), and voltage supervisors to stand-alone LVDS 

interface and buffers, and other related analog and mixedsignal 

technologies, including high-speed analog-to-digital 

converters (ADCs) and high-speed operational amplifiers. 

Step 1: 

Review the power requirements 

for your specific device 

Step 2: 

Choose the best National solution based 

on your specific operating conditions 

EP2S15 

V CCINT (V core) 1.20V 

I CCINT max (I core) 2A 

V CCIO options (V I/O) 3.3, 2.5, 1.8, 1.5V 

I CCIO max (I I/O) 10A (all 8 banks) 

V CCINT 

V CCINT = 1.2V 

V IN = 12V 

I CCINT < 1000 mA (LDO) Not applicable 1 

I CCINT < 1000 mA (SW) 

LM2734 

I CCINT < 3A 

LM2673-Adj 

I CCINT < 5A LM2679-Adj 2 or LM2743 3 

I CCINT < 7A LM2743 or 1 / 2 LM2647 4 




2

Selecting the best power architecture 

What is the best power architecture to use? 

Linear regulators 

Linear regulators are some of the simplest, easiest-to-use 

regulators available. To operate, these devices typically need 

only two external components — an input and an output 

capacitor. They also feature very clean low-noise outputs. The 

main disadvantage of the linear regulator architecture is power 

dissipation. When using a linear regulator, the power that is 

no longer needed at the output is simply dissipated as heat. 

When this dissipated power is less than 1W or 2W (max.), 

the solution can be surface-mounted and implemented 

without a heatsink if using an adequate package for the 

regulator. However, for dissipated power P D > 2W, a linear 

regulator architecture is usually not recommended because 

temperature rise, system efficiency, and overall solution space 

are better addressed using a different topology. 

For linear regulators, dissipated power can be estimated 

as (V IN – V OUT ) * I OUT . For a 5.0V to 3.3V conversion 

at 500 mA, P D is roughly (5.0 – 3.3) * 0.5 = 0.85W. 

Typically, linear regulators do not offer an option to adjust 

the turn-on rate (softstart) and thus may require additional 

external circuitry to implement this functionality. 

Switching regulators 

Switching regulators offer a consistent efficiency (typically 

85% to 95%) under most operating conditions (V IN , V OUT , 

I OUT ). Unlike their linear counterparts, these devices offer 

high efficiency, low heat dissipation, and the ability to stepup 

or step-down a voltage. Generally, a switching regulator 

uses an inductor in addition to input/output capacitors. 

Other external components might also be needed based on 

the specific topology used and functionality required. 

Buck regulators 

Buck regulators are the simplest step-down switching 

regulators to use. They offer good efficiency and low 

external component count (diode, inductor, and input/ 

output capacitors, at a minimum). Most National 

buck regulators (particularly those from the SIMPLE 

SWITCHER ® family) offer free online design tools, as 

well as electrical and thermal simulation. 

Synchronous buck converters 

Synchronous-rectification buck converters are a variation 

of standard buck regulators. The main difference is that 

the diode placed between the switch node and ground 

(catch diode) is replaced with a second active switch 

(MOSFET or bipolar transistor), reducing the power loss 

at this element. This is an important enhancement when 

the output current is high and when the diode dissipates a 

significant amount of power as heat. For output currents >5A, 

a synchronous buck converter is always recommended. 

As with standard buck regulators, synchronous buck 

converters are offered with monolithic (integrated) pass 

transistors or can use external ones. The advantage of using 

an external pass device (MOSFET or Bipolar) is more 

evident for output currents >3A, when there is a need to 

get very low RDS ON pass devices, distribute heat dissipation 

in more than one element around the board, and attain a 

cost-effective solution. 

Figure 1 shows a summary and a comparison of the three 

main power architecture solutions discussed above that are 

suitable for FPGA power. 

Buck Synchronous buck Linear regulator 

Function: Step-down (V OUT < V IN ) 

When to use: Typically when V IN is 3x to 5x V OUT 

and I OUT is > 0.5A and < 5A 

Characteristics: Easy to design and good efficiency 

for the above-mentioned typical V IN /V OUT /I OUT 

conditions 

Devices to use: All buck integrated regulators 

and controllers 


When to use: When high efficiency is required with 

high-output current (> 5A) or low duty cycles (V IN > 

5 x V OUT and/or I OUT < 0.5A) 

Characteristics: A second switch replaces the diode 

in the basic buck topology, reducing losses in the 

conditions mentioned above 

Devices to use: Any “synchronous rectification” 

buck integrated regulator or controller 

Figure 1. Step-down configurations 


When to use: Typically when I OUT < 1A, ultra 

low-dropout, and low-noise applications) 

Characteristics: Excellent option where fixed 

output, low current, and low voltage drops are 

required. Easy to implement 

Devices to use: Any low-dropout, linear regulator 

Comments: Great for micropower applications 

3

National power solutions for Stratix II FPGAs 

Stratix II FPGAs 

Stratix II FPGAs are Altera’s highest-density, highestperformance 

devices. Built on a 90-nm process technology, 

they incorporate a new logic structure that on average 

delivers 50% faster core performance with more than twice 

the logic capacity and costs 40% less than first-generation 

Stratix devices. Support is implemented for internal clock 

frequency rates of up to 500 MHz and typical design 

performance at over 250 MHz. 

Based on a 1.2V SRAM process, Stratix II devices are available 

in densities ranging from 15,600 to 179,400 equivalent 

logic elements (LEs) and up to 9 Mbits of on-chip RAM. 

Stratix II devices offer up to 384 (18-bit x 18-bit) embedded 

multipliers in highly optimized digital signal processing 

(DSP) blocks and source-synchronous differential signaling 

with dedicated dynamic phase alignment (DPA) circuitry 

operating at up to 1 Gbps. 

The core of these FPGAs needs to be powered from a 1.20V 

source. This voltage (V CCINT ) should always be within 

1.15V and 1.25V during regular operation. Core current 

consumption (I CCINT ) depends upon utilization of the part 

(such as clock speed and internal elements used). 

The I/O banks of this FPGA family are compatible with 

multiple standards, thus the supply voltage (V CCIO ) can 

either be 1.5V, 1.8V, 2.5V or 3.3V for one or more banks. 

Current consumption for the I/Os also depends upon the 

utilization of these elements, however for all I/O banks 

operating together, the max I CCIO for the Stratix II FGPA 

is 10A (independent of the V CCIO voltage used). 

Another power management consideration that needs 

to be addressed is the monotonic rise of V CCINT . This 

consideration is critical for the correct operation of the 

FPGA. While many power supplies take this requirement 

into consideration, it is recommended to further support 

this requirement by the use of adequate bulk capacitance 

in the power supply. 

LM2743 Low-voltage synchronous buck controller 

• Highly efficient 2A to 25A solution in SMD 

• Input voltage from 1V to 16V 

• Adjustable output voltage as low as 0.6V 

• Power-good flag and output enable 

• Output under-voltage and over-voltage flag 

• 1.5% reference accuracy over temperature 

• Current limit without sense resistor 

• Programmable softstart 

• Switching frequency from 50 kHz to 2 MHz 

• Available in small TSSOP-14 packaging 

 

 

 

 

 

LM2743 Typical application diagram 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Ideal for operation from 3.3V or 5V supplies in FPGA, DSP, and 

other high-current core regulator applications 

4

Stratix II FPGAs 

Stratix II power requirements summary 

EP2S15 EP2S30 EP2S60 EP2S90 EP2S130 EP2S180 

V CCINT (V core) 1.20V 1.20V 1.20V 1.20V 1.20V 1.20V 

I CCINT max (I core) 

Dynamic power consumption is design dependent. For accurate estimates, use Altera’s suite of PowerPlay power estimation tools. 

For more information: www.altera.com/support/devices/estimator/pow-powerplay.html 

V CCIO options (V I/O) 3.3, 2.5, 1.8, 1.5V 3.3, 2.5, 1.8, 1.5V 3.3, 2.5, 1.8, 1.5V 3.3, 2.5, 1.8, 1.5V 3.3, 2.5, 1.8, 1.5V 3.3, 2.5, 1.8, 1.5V 

National power solutions 

for Stratix II FPGAs 

V IN = 3.3V V IN = 5V V IN = 12V 5 

V CCINT 


I CCINT < 1000 mA (LDO) LP3875-Adj Not applicable 1 Not applicable 1 

I CCINT < 1000 mA (SW) LM2734 LM2734 LM2734 

I CCINT < 3A LM3475 LM3475 LM2673-Adj 

I CCINT < 5A LM2743 LM2743 LM2679-Adj 2 or LM2743 3 

I CCINT > 6A LM2743 LM2743 or 1 / 2 LM2657 4 LM2743 or 1 / 2 LM2657 4 

V CCIO 

V CCIO = 1.5V 

V CCIO = 1.8V 

V CCIO = 2.5V 

V CCIO = 3.3V 

I CCIO < 500 mA (LDO) LP3874-Adj LP3874-Adj Not applicable 1 

I CCIO < 500 mA (SW) LM3671-1.5 LM3671-1.5 LM2736 

I CCIO < 1000 mA (LDO) LP3875-Adj Not applicable 1 Not applicable 1 

I CCIO < 1000 mA (SW) LM2734 LM2734 LM2734 

I CCIO < 3A LM3475 LM2599-Adj 2 or LM2650-Adj 3 LM2673-Adj 2 or LM2650-Adj 3 

I CCIO < 5A LM2743 LM2743 LM2679-Adj 

I CCIO > 6A LM2743 LM2743 or 1 / 2 LM2657 4 LM2743 or 1 / 2 LM2657 4 

I CCIO < 500 mA (LDO) LP3874-1.8 LP3874-1.8 Not applicable 1 


I CCIO < 1000 mA (LDO) LP3875-1.8 Not applicable 1 Not applicable 1 






I CCIO < 500 mA (SW) LM3671-Adj LM3671-Adj LM2736 






I CCIO < 500 mA (LDO) — LP3874-3.3 Not applicable 1 

I CCIO < 500 mA (SW) — LM3671-Adj LM2736 


I CCIO < 1000 mA (SW) — LM2734 LM2734 

I CCIO < 3A — LM2599-3.3 2 or LM2650-Adj 3 LM2673-3.3 2 or LM2650-Adj 3 

I CCIO < 5A — LM2743 LM2679-3.3 

I CCIO > 6A — LM2743 or 1 / 2 LM2657 4 LM2743 or 1 / 2 LM2657 4 

V CCPD 

V CCPD = 3.3V 

I CCPD < 300 mA (LDO) — LP3981-3.3 Not applicable 1 

I CCPD < 300 mA (SW) — LM3670-3.3 LM2736 

1 

LDO option not applicable due to thermal constraints (heat dissipation) for the given operating conditions. 

2 

Buck regulator. Good efficiency, simple implementation, with WEBENCH design tools available. 

3 

Synchronous buck converter. Maximum efficiency, no external diode required. 

4 

One half of a dual converter, such as the LM2657, can be used to power V CCINT while the other half can be used to power V CCIO . 

5 

These solutions can be used with input voltages from 8V to 14V. 

5

National power solutions for Stratix FPGAs 

Stratix FPGAs 

The Stratix FPGA family is optimized to address the 

challenges of high-bandwidth systems. Stratix devices offer 

very high core performance, memory capacity, architectural 

efficiencies, and time-to-market advantages. Stratix devices 

offer dedicated functionality for clock management and 

digital signal processing (DSP) applications, as well as 

support for differential and single-ended I/O standards. 

In addition, Stratix devices offer on-chip termination and 

remote system upgrade capabilities. 

Based on a 1.5V, 0.13-µm, all-layer copper SRAM process, 

Stratix devices are available in densities ranging from 

10,570 to 79,040 logic elements (LEs) and up to 7 Mbits 

of RAM. Stratix devices offer up to 22 DSP blocks with 

up to 176 (9-bit x 9-bit) embedded multipliers, optimized 

complex applications that require high data throughput. 


source. Core current consumption (I CCINT ) depends upon 

utilization of the part (such as clock speed and internal 

elements used), but maximum values range from 1.5A to 

10A (approx.) depending on the specific Stratix device 

used. To calculate the most accurate power consumption 

values needed by a specific design, use Altera’s Power 

Calculator tool (see www.national.com/see/alterafpga). As 

a general rule, choose a V CCINT power supply whose I OUT 

(I CCINT ) capability is within the I CCINT inrush and I CCINT 

maximum values given in this guide for the specific Altera 

device used. 

Another power management consideration that needs 

to be addressed is the monotonic rise of V CCINT . This 

consideration is critical for the correct operation of the 

FPGA. While many power supplies take this requirement 

into consideration, it is recommended to further support 

this requirement by the use of adequate bulk capacitance 

in the power supply. 

LM2647 Dual synchronous buck controller 

• Input voltage range from 5.5V to 28V 

• Synchronous dual-channel interleaved 

switching 

• PWM or pulse-skip modes 

• Low-side MOSFET current sensing 

• Adjustable output voltage down to 0.6V 

• Power-good flag and chip enable 

• Under-voltage lockout hysteresis 

• Over-voltage/under-voltage protection 

• Softstart and soft-shutdown 

• Switching frequency adjustable from 

200 kHz to 500 kHz 

• Available in TSSOP-28 and tiny, 

thermally enhanced LLP-28 packaging 

LM2647 Efficiency curve 

Ideal for powering high-current V CCINT and V CCIO FPGAs from the 

same switching controller 

6

Stratix FPGAs 

Stratix power requirements summary 

EP1S10 EP1S20 EP1S25 EP1S30 EP1S40 EP1S60 EP1S80 

V CCINT (V core) 1.5V 1.5V 1.5V 1.5V 1.5V 1.5V 1.5V 

I CCINT max 5 (I core) 1.5A 3.5A 4A 5.5A 6A 7.5A 10A 

I CCINT inrush 

(startup inrush max) 

700 mA 1.2A 1.5A 1.9A 2.3A 2.6A 3A 

V CCIO options (V I/O) 3.3, 2.5, 1.8, 1.5V 3.3, 2.5, 1.8, 1.5V 3.3, 2.5, 1.8, 1.5V 3.3, 2.5, 1.8, 1.5V 3.3, 2.5, 1.8, 1.5V 3.3, 2.5, 1.8, 1.5V 3.3, 2.5, 1.8, 1.5V 

I CCIO max (I I/O) 12A (all 8 banks) 12A (all 8 banks) 12A (all 8 banks) 12A (all 8 banks) 12A (all 8 banks) 12A (all 8 banks) 12A (all 8 banks) 


for Stratix FPGAs 

V IN = 3.3V V IN = 5V V IN = 12V 6 

V CCINT 




I CCINT < 3A LM3475 LM2599-Adj 2 or LM2650-Adj 3 LM2673-Adj 2 or LM2650-Adj 3 


I CCINT < 7.5A LM2743 LM2743 LM2743 or 1 / 2 LM5642 4 

I CCINT < 10A LM2743 LM2743 LM2743 or 1 / 2 LM5642 4 

V CCIO 

V CCIO = 1.5V 

V CCIO = 1.8V 

V CCIO = 2.5V 

V CCIO = 3.3V 






I CCIO < 5A LM2743 LM2743 LM2679-Adj 2 or LM2743 3 

I CCIO > 6A LM2743 LM2743 LM2743 or 1 / 2 LM5642 4 




















I CCIO < 5A — LM2743 LM2679-Adj 2 or LM2743 3 

I CCIO > 6A — LM2743 LM2743 or 1 / 2 LM5642 4 

1 


2 


3 


4 


5 

Estimated values. Actual power consumption figures are dependant upon a broad number of operating conditions. Use Altera’s Power 

Calculator tool for the most accurate calculation of the power requirements for your specific design. 

6 


7

National power solutions for Cyclone FPGAs 

Cyclone FPGAs 

Altera’s Cyclone series of FPGAs provides the benefits of 

programmable logic at price points competitive with ASICs 

and ASSPs. Built from the ground up based on extensive 

input from hundreds of customers, these low-cost devices 

provide high-volume, application-focused features such as 

embedded memory, external memory interfaces, and clock 

management circuitry. Based on the cost-optimized all-layer 

copper 1.5V SRAM process, Cyclone FPGAs are available 

in densities ranging from 2,910 to 20,060 logic elements 

(LEs) with up to 294,912 bits of embedded RAM. 

Cyclone FPGAs support a variety of single-ended I/O 

standards such as LVTTL, LVCMOS, PCI, and SSTL-2/3 

and offer differential I/O support via the LVDS and RSDS 

I/O standards on up to 129 channels. Each channel is 

capable of operating LVDS signals at up to 640 Mbps. 

Cyclone devices feature dedicated circuitry to implement 

double data rate (DDR) SDRAM and FCRAM interfaces. 

LM2734/36 1A SOT-23 buck regulators 

• Complete, easy-to-use switcher solution has 

smallest footprint and highest power density in 

the industry 

• State-of-the-art 13 ns minimum ON-time allows 

for high conversion ratios without the need to 

reduce switching frequency or increase solution size 

• Choice of switching frequencies allows designers 

to trade off efficiency against solution size and EMI 

• Current mode control improves phase margin, line 

regulation and rejection of transients 

• PWM provides a predictable, easily filtered 

switching frequency for reduced output noise 

• Internal softstart circuitry, cycle-by-cycle, thermal 

shutdown, and over-voltage protection 

• Available in TSOT-23 packaging (1.0 mm height) 


source. Core current consumption (I CCINT ) depends upon 

utilization of the part (such as clock speed and internal 

elements used), but maximum values range from 0.75A 

to 5A (approx.) depending on the specific Cyclone device 

used. To calculate the most accurate power consumption 

values needed by a specific design, use Altera’s Power 

Calculator tool (see www.national.com/see/alterafpga). As 

a general rule, choose a V CCINT power supply whose I OUT 


maximum values given in this guide for the specific Altera 

device used. 

Another power management consideration is the monotonic 

rise of V CCINT . This consideration is critical for the correct 

operation of the FPGA. While many power supplies take 

this requirement into consideration, it is recommended to 

further support this requirement by the use of adequate 

bulk capacitance in the power supply. 

 

 

 

 

 

 

 


 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Feature LM2734 LM2736 

Input range 3.0V to 20V 3.0V to 18V 

Output load 1A 750 mA 

Output range 0.8V to 18V 1.25V to 16V 

Internal references 0.8V, 2% 1.25V, 2% 

Operating frequency 

550 kHz / 1.6 MHz / 3 MHz 

 

 

 

 

8


Cyclone power requirements summary 

EP1C3 EP1C4 EP1C6 EP1C12 EP1C20 

V CCINT (V core) 1.5V 1.5V 1.5V 1.5V 1.5V 

I CCINT max 5 (I core) 750 mA 1A 1.5A 3A 5A 

I CCINT inrush (startup inrush max) 300 mA 400 mA 500 mA 900 mA 1.2A 

V CCIO options (V I/O) 3.3, 2.5, 1.8, 1.5V 3.3, 2.5, 1.8, 1.5V 3.3, 2.5, 1.8, 1.5V 3.3, 2.5, 1.8, 1.5V 3.3, 2.5, 1.8, 1.5V 

I CCIO max (I I/O) 6A (all 4 banks) 6A (all 4 banks) 6A (all 4 banks) 6A (all 4 banks) 6A (all 4 banks) 


for Cyclone FPGAs 

V IN = 3.3V V IN = 5V V IN = 12V 6 

V CCINT 


I CCINT < 500 mA (LDO) LP3874-Adj LP3874-Adj Not applicable 1 

I CCINT < 500 mA (SW) LM3671-1.5 LM3671-1.5 LM2736 



I CCINT < 3A LM3475 LM2599- Adj 2 or LM2650-Adj 3 LM2673-Adj 2 or LM2650-Adj 3 


V CCIO 

V CCIO = 1.5V 

V CCIO = 1.8V 

V CCIO = 2.5V 

V CCIO = 3.3V 







I CCIO < 6A LM2743 LM2743 LM2743 or 1 / 2 LM5642 4 












I CCIO < 3A LM3475 LM2599-Adj 2 or LM2650-Adj 3 LM2673-Ad j2 or LM2650-Adj 3 








I CCIO < 5A — LM2743 LM2679-Adj 2 or LM2743 3 

I CCIO < 6A — LM2743 LM2743 or 1 / 2 LM5642 4 

1 


2 


3 


4 


5 

Estimated values. Actual power consumption figures are dependant upon a broad number of operating conditions. 

Use Altera’s Power Calculator tool for the most accurate calculation of the power requirements for your specific design. 

6 


9

National power solutions for MAX II CPLDs 

MAX II CPLDs 

The MAX II CPLD family is a non-volatile, instant-on 

programmable logic family with a new CPLD architecture, 

which allows significant power and density enhancements 

from previous MAX devices. Based on a 0.18-µm Flash 

process, the MAX II devices offer densities ranging from 240 

to 2,210 logic elements (LEs) and up to 272 user I/O pins. 

The core of these CPLDs (V CCINT ) needs to be powered from 

a 1.8V source. The non-G versions of MAX II devices have 

an internal voltage regulator and the V CCINT pin can accept 

either 3.3V or 2.5V. This internal regulator steps down 

the voltage to the needed 1.8V. On the G-version MAX II 

CPLDs, the internal regulator is bypassed and V CCINT needs 

to be only 1.8V. Core current consumption (I CCINT ) depends 

upon utilization of the part (such as clock speed and internal 

elements used), but typical values range from 30 mA to 75 

mA with maximum values in the 75 mA to 400 mA range. 

Typically, operating core current (I CCINT ) for MAX II devices 


for MAX II CPLDs 

will be 10 mA less in the 1.8V G versions. The I/O current 

(I CCIO ) also depends upon the device utilization, with typical 

values in the 100 mA to 200 mA range. Maximum values can 

reach 225 mA per bank or 900 mA total for up to four banks. 

To calculate the most accurate power consumption values 

needed by your specific design, we recommend using 

Altera’s Power Calculator tool, available online. A good rule 

of thumb is to choose a V CCINT power supply whose I OUT 


maximum values. As opposed to FPGAs, these CPLDs do 

not have specific requirements for monotonic voltage rise or 

V CCINT rise times. Since MAX II CPLDs consume low power, 

the use of LDOs and inductorless switching regulators is 

recommended. For LDOs, it is advised to check the thermal 

dissipation capability of the part based on the package and 

the operating conditions. It is not enough to check V IN , V OUT 

and I OUT alone for selecting LDOs. The LDOs recommended 

in the following tables address thermal dissipation capabilities. 

V IN = 3.3V V IN = 5V V IN = 12V 

V CCINT 




I CCIO < 100 mA (LDO) LP3990-1.8 LP3990-1.8 LP2992-1.8 5 

I CCIO < 100 mA (SW) LM2798-1.8 4 LM2798-1.8 4 LM2736 









I CCIO < 100 mA (LDO) LP3990-2.5 LP3990-2.5 LM2937-2.5 or LP2992-2.5 5 









I CCIO < 500 mA (SW) LM3671-Adj 3 LM3671-Adj 3 LM2736 

I CCIO < 100 mA (LDO) — LP3990-3.3 LM2937-3.3 or LP2986-3.3 5 

I CCIO < 100 mA (SW) — LM3352-3.3 4 LM2736 








I CCIO < 500 mA (SW) — LM3671-Adj 3 LM2736 

10


MAX II power requirements summary 

EPM240 EPM240G EPM570 EPM570G EPM1270 EPM1270G EPM2210 EPM2210G 

V CCINT (V core) 3.3 or 2.5V 1.8V 3.3 or 2.5V 1.8V 3.3 or 2.5V 1.8V 3.3 or 2.5V 1.8V 

I CCINT max 5 (I core) 75 mA 75 mA 125 mA 125 mA 250 mA 250 mA 400 mA 400 mA 

I CCINT inrush 

(startup inrush max) 

65 mA 55 mA 65 mA 55 mA 65 mA 55 mA 65 mA 55 mA 

V CCIO options (V I/O) 3.3, 2.5, 1.8, 1.5V 3.3, 2.5, 1.8, 1.5V 3.3, 2.5, 1.8, 1.5V 3.3, 2.5, 1.8, 1.5V 3.3, 2.5, 1.8, 1.5V 3.3, 2.5, 1.8, 1.5V 3.3, 2.5, 1.8, 1.5V 3.3, 2.5, 1.8, 1.5V 

I CCIO max (I I/O) 

450 mA 

(both banks) 

450 mA 

(both banks) 

450 mA 

(both banks) 

450 mA 

(both banks) 

900 mA 

(all 4 banks) 

900 mA 

(all 4 banks) 

900 mA 

(all 4 banks) 

900 mA 

(all 4 banks) 


for MAX II CPLDs (cont.) 

V IN = 3.3V V IN = 5V V IN = 12V 6 

V CCIO 

V CCIO = 1.5V 

V CCIO = 1.8V 

V CCIO = 2.5V 

V CCIO = 3.3V 

I CCIO < 100 mA (LDO) LP3990-1.5 LP3990-1.5 LP2986-Adj 5 






I CCIO < 500 mA LM3671-1.5 3 LM3671-1.5 3 LM2736 

I CCIO < 750 mA LM2736 LM2736 LM2736 

I CCIO < 1A LM2734 LM2734 LM2734 







I CCIO < 500 mA LM3671-1.8 3 LM3671-1.8 3 LM2736 


I CCIO < 1A LM2734 LM2734 LM2734 







I CCIO < 500 mA LP2989-2.5 LM3671-Adj 3 LM2736 


I CCIO < 1A LM2734 LM2734 LM2734 







I CCIO < 500 mA — LP8345-3.3 LM2736 

I CCIO < 750 mA — LM2736 LM2736 

I CCIO < 1A — LM2734 LM2734 

1 


2 


3 


4 

Inductorless switching regulator. 

5 

Use LLP package for adequate thermal dissipation. 

6 


11

Design considerations for powering FPGAs & CPLDs 

Bulk capacitance 

In any power supply, the output capacitors are a vital 

element for adequate performance. They are used to 

control the output voltage ripple (ΔV OUT ) and to supply 

load current during fast load transients. Various types 

of capacitors may be used. However, the ceramic type 

often do not have the large capacitance needed to supply 

current for load transients, and tantalums tend to be more 

expensive than aluminum electrolytic. 

Adding bulk capacitance to the output of high-current 

switching supplies is always recommended and is also very 

important for adequate FPGA performance. Bulk capacitance 

helps provide current during start-up transients, thus 

supporting an adequate monotonic voltage rise in highcurrent 

power supplies. More in-depth recommendations 

on the use and benefits of bulk capacitance in FPGA 

power supplies are available in Altera’s application note 

AN-355 (see page 23 for download information). 

Layout 

FPGA power design can involve very high currents (5A, 

10A, and 15A are common) flowing in the traces of the 

PCB. When these larger currents are present and change 

over time in a switching pattern with sharp edges, it is easy 

to realize that noise, induced voltages, and EMI may be 

present and may cause undesirable behavior in the power 

supply if proper care is not taken. This is why proper layout 

is critical in every switching regulator design. Rapidly 

switching currents associated with wiring inductance can 

also generate voltage transients which may cause additional 

problems. For minimal inductance and ground loops, 

the PCB traces conducting high current and/or switching 

waveforms should be kept as short as possible. 

For best results, external components should be located as 

close to the switcher IC as possible, using ground-plane 

construction or single-point grounding. If open core 

inductors are used, special care must be taken as to the 

location and positioning of this type of inductor. Allowing 

the inductor flux to intersect sensitive feedback IC ground 

path and C OUT wiring can cause problems. 

When using a switching regulator or controller with an 

adjustable output, special care must be taken as to the 

location of the feedback resistors and the associated wiring. 

Physically locate both resistors near the IC and route the 

wiring away from the inductor, especially an open core 

type of inductor. Ferrite bobbin or stick inductors have 

magnetic lines of flux flowing through the air from one 

end of the bobbin to the other end. These magnetic lines 

of flux will induce a voltage into any wire or PC board 

copper trace that comes within the inductor’s magnetic field. 

The strength of the magnetic field, the orientation and 

location of the PC copper trace to the magnetic field, and 

the distance between the copper trace and the inductor 

determine the amount of voltage generated in the copper 

trace. For a deeper understanding of buck converters 

and PCB layout guidelines around them, see National’s 

application notes AN-1149 and AN-1229 (see page 23 for 

download information). 

Softstart 

As with most digital systems, FPGAs need their supply voltage 

to rise from zero to full voltage within a specified period of 

time. Altera FPGAs are very flexible and the requirements 

are not difficult to meet, but start-up timing still needs to 

be observed. For example, Stratix II FPGAs need V CCINT to 

rise in a window anywhere from 30 µs to 100 ms. To achieve 

that controlled rise time, softstart in the power supply must 

be used. Most switching regulators and controllers already 

have softstart incorporated, either internally fixed or externally 

programmable. When user programmable, a softstart pin (SS) 

is available and softstart timing is typically adjusted by placing 

a small capacitor between that pin and ground. Depending on 

the capacitor value, the softstart time will change. 

Information on which capacitor values to use and how to 

calculate the needed value to achieve a particular ramp-up 

time is described on each switching regulator’s datasheet. 

For linear regulators where softstart is not typically an 

internally implemented function, an external pass device 

is used along with a resistor and a capacitor to achieve this 

same effect. 

12

Monotonic voltage rise 

Although not typically required in CPLDs, most FPGAs 

need the supply voltage to turn on steadily and gradually. 

This is called monotonic voltage rise and is needed for 

internal elements in the FPGA to turn on sequentially as 

the input voltage rises. As these elements are turning on 

during the ramp-up period, the “load” to the power supply 

will not be constant, so it is important that the power 

supply chosen regulates its output voltage not only during 

steady state but also during ramp up. As mentioned before, 

bulk capacitance is also a very important element for 

ensuring that the power supply has an adequate monotonic 

rise for powering FPGAs. 

The figure below shows the monotonic rise achieved in 

V OUT when using National’s LM2743 switching controller 

to power a Stratix II FPGA. The LM2743 power supply 

design used for this graph is included in the reference 

design section of this guide. 

 

 

 

 

LM2743 V OUT monotonic rise 

 

 

Selecting the best power solution for Altera devices 

Depending on the operating conditions and the specific 

Altera device used, all three of the power topologies 

previously mentioned (linear, buck, and synchronous buck) 

come into play. As seen throughout the selection tables, a 

choice of either an LDO or a switching regulator solution 

is provided for relatively small output currents in FPGAs 

(500 mA and 1A). The exception is when the input-tooutput 

voltage ratio is high and an LDO solution is no 

longer suitable because of high thermal dissipation (e.g., 

12V to 3.3V @ 500 mA or 5V to 1.2V @ 1A). For output 

currents >5A, synchronous buck controllers are always 

recommended as they provide the best option in terms of 

efficiency, heat dissipation, performance, and cost. 

CPLDs are low-power devices. As seen in the MAX II 

solutions table, most of the power supplies recommended 

are LDOs and monolithic (integrated) switching regulators 

because typical current requirements are always below 

1A. One alternative for high efficiency and simple, hasslefree 

design is to use inductorless switching regulators. 

These devices provide efficiencies in the 80% range, thus 

dissipating very small amounts of power as heat. As implied 

by their name, these devices do not require an inductor 

(only small external capacitors) and are as easy to use as 

linear regulators. Inductorless switching regulators are a good 

option for powering loads in the 10 mA to 250 mA range. 

For all digital supplies needed by the FPGA (such as 

V CCINT and V CCIO ), either a switching or a linear solution 

is sufficient. When the supply is powering an analog FPGA 

block (V CCPLL , for example) a linear solution is usually 

recommended as it has a cleaner low-noise output. 

 

13

Reference designs 

Stratix II & Stratix FPGAs 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Stratix II/Stratix* Complete Power Supply Reference Design 

(5V in, 1.20V @ 9A, 2.5V @ 6A and 3.3V @ 0.3A out) 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

This reference design features the high-current, low inputvoltage 

LM2743 synchronous buck switching controller 

and the low-power LP3981 LDO to offer a complete 

power supply solution for a typical Stratix II application. 

The LM2743 can be used for output currents from 1A 

up to 25A. Output voltage on this part can be adjusted 

anywhere down to 0.6V. For this Stratix II design, the 

output voltage has been programmed in the LM2743 to 

supply 1.20V for V CCINT and 2.5V for V CCIO . This same 

reference design can be used for Stratix FPGAs by simply 

changing V CCINT to 1.5V. This can be done by changing 

R8 from 2 kΩ to 1.33 kΩ. 

In the following pages you will find various V CCINT and 

V CCIO reference designs that can be used in different 

combinations to provide the most adequate power supply 

solution for different I CCINT and I CCIO requirements when 

powering Altera’s Stratix II, Stratix, and Cylcone FPGAs. 

For additional information on these reference designs, 

such as complete bills of material, test waveforms, and 

performance reports, visit: 


14


 

Stratix II/Stratix/Cyclone V CCINT Power Supply Reference Design 

(3.3V in, 1.20V* out @ 4A) 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

This V CCINT LM2743-based reference designs shows how an 

up-to-4A V CORE solution for Stratix II can be implemented 

from a 3.3V source. Because the LM2743 has a V CC from 

3.0V to 6.0V, no special considerations need to be taken to 

have this circuit work from 3.3V directly. While ideal for 

powering the EP2S15 Stratix II FPGA, this design can also 

be utilized to power various Stratix and Cyclone devices, 

such as the EP1S10, EP1S20, EP1S25 and EP1C12 by 

changing the LM2743 output voltage (V CCINT ) from 1.20V 

to 1.5V. This is done simply by changing R6 from 2 kΩ to 

1.33 kΩ. 

 

Stratix II/Stratix V CCINT Power Supply Reference Design 

(12V in, 1.2V*out @ 9A) 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

This other LM2743-based V CCINT reference design shows 

how a Stratix II or Stratix FPGA can be powered at 

high current (up to 9A) from a 12V supply. Because the 

LM2743 has a V IN range from 1V to 16V, the 12V input 

voltage in this application is taken directly to the power 

train of this switching converter formed by the power 

MOSFETs and the inductor. The LM2743 is biased from 

a 5V rail at merely 1 mA typical or 3 mA maximum. 

The I CCINT (I OUT ) from this design is ideally suited to power 

the EP2S90 and the EP2S60 Stratix II FPGAs. This design 

can also power the EP1S60 and EP1S80 Stratix devices if 

V CCINT is programmed to 1.5V. This is done by changing 

R6 in this design to 1.33 kΩ. 





15



 

Stratix II V CCINT Power Supply Reference Design 

(5V in, 1.20V out @ 16A) 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

This third LM2743-based V CCINT reference design features 

a high-current I CCINT output with an up to 16A capability 

to ideally power the EP2S180 and the EP2S130 Stratix II 

FPGAs. It can also be used to power the EP1S80 Stratix 

device, making the V CCINT 1.5V. As previously described in 

the “Powering FPGA Design Considerations” section, it is 

highly recommended to place proper bulk capacitance in 

the output of the power supply when large I CCINT current 

is involved. This is needed for the adequate performance 

of the FPGA during load transient conditions and also to 

help in proper start-up of the device during power up. 

 

 

Stratix II/Stratix V CCIO 3A to 10A Power Supply Reference Design 

(5V in, 1.8V out @ 10A) 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

The I/O banks in FPGAs can be powered at different 

V CCIO voltages depending on the I/O standard at which 

they will be used. Different I/O banks in the same FPGA 

may be powered with different V CCIO voltages to work on 

different I/O standards simultaneously. 

The present LM2743-based design shows a high-current 

power supply to power V CCIO at a typical 1.8V and has an 

I OUT capability of up to 10A. Such high current is needed 

by Stratix II or Stratix FPGAs when all banks (up to 8) are 

fully utilized and powered from the same V CCIO . However, 

this same power supply is adequate for powering I/O banks 

that require current (I CCIO ) anywhere from 3A to 10A. 





16


 

Stratix II/Stratix/Cyclone V CCIO 3A to 10A Power Supply Reference Design 

(5V in, 3.3V out @ 10A) 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

This synchronous buck design featuring the LM2743 

shows a high-current power supply to power V CCIO at the 

very common 3.3V rail from a 5V supply. It has an I OUT 

capability of up to 10A, however the design can be used in 

any application needing from 1A to 10A of current. For 

3A and up, the use of a synchronous buck controller (such 

as this one) is highly recommended. 

 

Stratix II/Stratix/Cyclone V CCIO 3A to 10A Power Supply Reference Design 

(12V in, 3.3V out @ 10A) 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

This flexible LM2743-based design shows a high-current 

power supply to power V CCIO at the very common 3.3V rail 

from a 12V supply. It has an I OUT capability of up to 10A, 

however it can be used in any application needing from 1A 

to 10A of current. For 3A and up, the use of a synchronous 

buck controller (such as the LM2743) is ideal. 





17



This complete reference design 

is based on National’s smallest 

new switching regulators. The 

LM2734 features up to 1A 

I OUT from a tiny Thin SOT-23 

package, while the LM3671 

(also in SOT-23) provides onboard 

synchronous rectification 

for maximum efficiency and 

the least number of external 

components. Both devices are 

available in high switching 

frequencies for small designs 

using tiny, passive elements. 

 

 

 

 

 

 

 

 

 

 

 

Cyclone Complete Power Supply Reference Design 

(3.3V in, 1.5V @ 1A and 1.8V @ 600 mA out) 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 


(5V in, 1.5V @ 1.5A and 2.5V @ 600 mA out) 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 


for Cyclone FPGAs utilizes the 

LM3671 and LM2651. Both 

synchronous buck switching 

regulators provide ultrahigh 

efficiency and require 

minimal external components. 

By changing R5, V CCIO can 

be adjusted to fit different 

requirements than 2.5V I/O 

standards. 

 

 

 


can be used for virtually any 

Cyclone FPGA. The wide V IN 

range (8V to 40V) allows the 

use of many industrial rails (12V, 

24V, 36V) as well as unregulated 

“wall warts.” Based on National’s 

SIMPLE SWITCHER ® regulator 

family, the LM267x provides 5A 

and 3A, while other members of 

the family have output currents 

of 2A, 1A, and 0.5A. The 

LM267x family is available in 

LLP packaging and WEBENCH 

design tools are available. 

 

 

 

 

 

 

 

 

 


(12V in, 1.5V @ 5A and 3.3V @ 3A out) 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

18


 

 

MAX II Complete Power Supply Reference Design 

(High-efficiency inductorless switching regulator based) 

(5V in, 2.5V out @ 200 mA) 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

This complete MAX II design features the 

LM3352, one of National’s inductorless 

high-efficiency switching regulators. With 

only tiny ceramic capacitors as external 

components, this device provides the required 

voltage to power both V CCINT and V CCIO with 

significantly better efficiency than that of 

LDOs. This IC also features useful automatic 

step-up and step-down capability. 

This complete MAX-II G reference design 

features two of the newest National regulators 

for portable power applications, the LP3990 

LDO and the LM2798 inductorless, highefficiency 

switching regulator to provide 

robust performance and a very small size 

solution. While an LDO is adequate for a 

5V to 3.3V conversion at low current, when 

output voltage is as low as 1.8V the use of a 

different architecture is needed to maintain high 

efficiency and to properly dissipate power in a 

tiny package without the usual temperature rise. 

MAX II-G Complete Power Supply Reference Design 

(High-efficiency inductorless switching regulator based for V CCINT ) 

(5V in, 1.8V out @ 120 mA and 3.3V @ 150 mA out) 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

MAX II Complete Power Supply Reference Design 

(Linear regualtor based) 

(5V in, 2.5V out @ 0.4A) 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

For additional information on these reference designs, such as complete 

bills of material, test waveforms, and performance reports, visit: 


This reference design for the MAX II CPLD 

utilizes an LP3871 LDO to step down the 

voltage from a 5V supply to 2.5V. This power 

supply has been put together for a MAX II 

device in an application driving a 2.5V I/O 

standard (V CCIO ). Since the MAX II (non-G 

version) can accept a V CCINT of either 3.3V or 

2.5V, a single power supply is being built with 

the LP3871 and leveraged for powering both 

V CCINT and V CCIO , providing a very compact 

and easy-to-implement solution. 

This design is fulfilling a 400 mA combined 

I CCINT and I CCIO current need (enough current 

for most MAX II designs). It can also be used 

for lower I CCINT currents and with proper 

thermal dissipation, this same design can 

output up to 800 mA utilizing only SMD 

components without any heatsink. 

19

Other technologies for FPGA/CPLD-based designs 

DDR memory solutions 

Product ID 

V IN range 

(P VIN ) 

Sink/source 

I OUT (A) 

Standards 

Temp 

range (°C) 

Other features/comments 

Packaging 

Memory supply (V DD /V DDQ ) regulators 

LM2727 2.2 to 16 0.5 to 20 cont. DDR & DDR-II -40 to 125 Suspend to disk shutdown; UVP & OVP latch-off TSSOP-14 

LM2737 2.2 to 16 0.5 to 20 cont. DDR & DDR-II -40 to 125 Suspend to disk shutdown TSSOP-14 

Memory termination (V TT ) and reference (V REF ) regulators — linear 

LP2996 1.5 to 5.5 3 peak, 1.5 cont. DDR & DDR-II 0 to 125 Suspend to RAM shutdown SO-8, LLP-16, PSOP-8 

LP2997 1.5 to 5.5 1.5 peak, 0.5 cont. DDR-II 0 to 125 Suspend to RAM shutdown SO-8, PSOP-8 

Memory termination (V TT ) and reference (V REF ) regulators — switching 

LM2744 1 to 16 0.5 to 25 cont. DDR & DDR-II -40 to 125 Suspend to RAM shutdown TSSOP-14 

Discrete LVDS buffers and transceivers 

Save FPGA I/O resources 

FPGA LVDS I/O resources are too valuable to waste on 

duplicate signals. The DS90LV110 makes up to 10 copies of 

your FPGA LVDS clock or data signals and distributes the 

high quality signals to multiple destinations. In addition, the 

family of LVDS-to-LVDS switches provide active and backup 

channels to enable highly available systems. 

 

 

Redundant cable drive application 

 

 

 

 

 

 

 

Improve LVDS performance and ESD protection 

Boost FPGA reach and rate with enhanced signal integrity 

and lower jitter. The SCAN90CP02 offers programmable 

pre-emphasis to drive CAT-5 cables. These products also 

deliver superior ESD protection. Designers can improve ESD 

protection by 2.5 kV to 6.5 kV by providing isolation for 

sensitive programmable devices. 

DS90LV110 1:10 LVDS clock distributor 

 

 

Simplified FPGA programming 

The SCANSTA111/112 SCAN chain mux simplifies FPGA 

programming by managing multiple JTAG chains. 

LVDS interface devices to complement FPGAs 

Product ID Description Max speed Packaging 

DS90CP22 2 x 2 LVDS-to-LVDS Crosspoint switch with >5 kV ESD 800 Mbps/channel SO-16, TSSOP-16 

SCAN90CP02 2 x 2 LVDS-to-LVDS Crosspoint switch with pre-emphasis, IEEE 1149.6 and >6.5 kV ESD 1.5 Gbps/channel LLP-28, LQFP-32 

SCAN50C400 Quad multi-rate, 1.25, 2.5, and 5.0 Gbps SerDes with 3.5 kV ESD 40 Gbps EBGA-440 

DS90CP04 4 x 4 LVDS-to-LVDS Crosspoint switch 2.5 Gbps/channel LLP-32 

DS90LV001 Stub hider LVDS/PECL to LVDS buffer with >2.5 kV ESD 800 Mbps LLP-8, SO-8 

DS92001 Signal booster LVDS/LVPECL to Bus LVDS buffer with >2.5 kV ESD 400 Mbps LLP-8, SO-8 

EQ50F100 2.5 Gbps to 6.125 Gbps equalizer for CML technology with 8 kV ESD 6.125 Gbps LLP-6 

DS90LV110A 1:10 LVDS clock distributor with >4 kV ESD 400 Mbps TSSOP-28 

20

High-speed data conversion ICs 

Product ID 

Resolution 

Speed 

(MSPS) 

Input 

channels 

Accuracy 

(INL) SINAD SNR SFDR THD Packaging 

ADC081000 8 1000 1 ±0.35 47 48 58.5 -57 TQFP-128 

ADC08200 8 200 1 ±1.0 46 46 60 -60 TSSOP-24 

ADC08L060 8 60 1 ±0.5 47.4 48 59.1 -56.9 TSSOP-24 

ADC1173 8 15 1 ±0.5 47.7 48.7 55 -54 SO-24, TSSOP-24 

ADC081S101 8 1 1 ±0.05 49.7 49.7 69 -77 SOT23-6, LLP-6 

ADC10080 10 80 1 ±0.5 59 59.2 78.8 -74.5 TSSOP-28 

ADC10065 10 65 1 ±0.3 59 59.3 80 -72 TSSOP-28 

ADC10D040 10 40 2 ±0.65 59 60 72 -69 TSSOP-28 

ADC101S101 10 1 1 ±0.2 61.7 62 78 -77 SOT23-6, LLP-6 

ADC12L080 12 80 1 ±1.2 66 66 80 -77 TQFP-32 

ADC12DL066 12 66 2 ±1.8 66 66 81 -78 TQFP-64 

ADC12D040 12 40 2 ±0.7 68 68 80 -78 TQFP-64 

ADC121S101 12 1 1 ±0.4 72 72.5 82 -82 SOT23-6, LLP-6 

ADC78H90 12 0.5 8 ±1.0 73 73 88 -86 TSSOP-16 

High-speed, low-power amplifiers 

Product 

ID 

SSBW 

(MHz) 

A V 

V/V 

Slew 

rate 

V/µs 

Spec. 

range (V) 

2nd/3rd HD 

into R L = 100Ω 

I OUT 

typ 

(mA) 

Voltage 

noise 

(nV/Hz) 

Key features 

Packaging 

LMH6609 

900 MHz high-output current voltage 

feedback 

900 1 1400 ±3.3 to ±6 -63/-57 at 20 MHz 90 3.1 SO-8, SOT23-5 

LMH6559 Ultra-high slew rate, closed-loop buffer 1750 1 4580 3 to ±5 -58/-53 at 20 MHz 74 2.8 SO-8, SOT23-5 

LMH6624 Ultra-low noise, wideband 1500/95 1/20 350 ±2.5 to ±6 -63/-80 at 10 MHz 100 0.92 SO-8, SOT23-5, CERDIP-8 

LMH6642 130 MHz, 75 mA rail-to-rail output 130 1 135 3 to 12.8 -62 at 5 MHz 75 17 SO-8, SOT23-5 

LMH6645 Rail-to-rail input/output, low power 55 1 22 2.5 to 12 — 20 17 SO-8, SOT23-5 

LMH6654 Low noise, 250 MHz, low power 250 1 200 ±2.5 to ±6 -80/-85 at 5 MHz 80 4.5 SO-8, SOT23-5 

LMH6657 270 MHz single supply, CMIR < 0V 270 1 700 3 to 12 -70/-57 at 5 MHz 110 11 SC70-5, SOT23-5 

LMH6702 Ultra-low distortion, wide bandwidth 720 2 3100 ±5 to ±6 -63/-70 at 60 MHz 80 1.83 SO-8, SOT23-5, CERDIP-8 

LMH6714 Wideband video 400 2 1800 ±5 to ±6 -58/-70 at 20 MHz 70 3.4 SO-8, SOT23-5, CERDIP-8 

LMH6723 370 MHz, 1 mA high-output current 260 2 600 4.5 to 12 -65/-63 at 5 MHz 110 4.3 SO-8, SOT23-5 

LMH6732 Adjustable supply current 540 2 2700 ±4.5 to ±6 -60/-64 at 20 MHz 115 2.5 SO-8, SOT23-6 

LM7171 30V, very high slew rate, A V = +2 (min) 220 2 4100 ±5.5 to ±15 -75/-55 at 5 MHz 100 14 SO-8, SOT23-5, CERDIP-8 

For more design information, please refer to these guides at www.national.com/guides 

LVDS Owner’s Manual 

Broadcast Video Owner’s Manual 

Ultra-fast ADCs and Amplifiers Guide 

For more LVDS information: 

LVDS.national.com 

For more interface information: 

national.com/appinfo/interface 

For more ADC or amplifiers information: 

national.com/adc 

amplifiers.national.com 

21

Product summary 

Recommended regulators 

Recommended V CCINT and V CCIO regulators summary 

Product 

ID 

V IN 

V OUT options for FPGAs/ 

CPLDs 

Min Max 

Inductorless switching regulators 

I OUT max 

Shutdown 

Sync. 

buck F SW (kHz) Comments Packaging 

LM2788 2.6 5.5 1.5, 1.8, 2.0 120 mA ✔ — 500 — MSOP-8 

LM2798 2.6 5.5 1.5, 1.8, 2.0 120 mA ✔ — 500 Power good flag MSOP-10 

LM3352 2.5 5.5 2.5, 3.0, 3.3 200 mA ✔ — 900 — TSSOP-16 

LM2770 2.7 5.5 1.2, 1.5 250 mA ✔ — 700 Sleep mode LLP-10 

Switching buck regulators 

LM3670 2.5 5.5 

1.2, 1.5, 1.8, 2.5, 3.3 & Adj (0.7V 

& up) 

350 mA ✔ ✔ 1000 — SOT23-5 

LM2619 2.8 5.5 Adj (1.5V & up) 500 mA ✔ ✔ 500 to 1000 — TSSOP-14 

LM2671 8 40 3.3 & Adj (1.21 & up) 500 mA ✔ — 260 to 400 WEBENCH Tool SO-8, LLP-16, DIP-8 

LM3671 2.5 5.5 1.2, 1.5, 1.8 & Adj (0.5V & up) 600 mA ✔ ✔ 2000 — SOT23-5 

LM2736 3 18 Adj (1.25V & up) 750 mA ✔ — 550, 1600, 3000 WEBENCH Tool SOT23-5 

LM2734 3 20 Adj (0.8V & up) 1000 mA ✔ — 550, 1600, 3000 WEBENCH Tool SOT23-5 

LM2651 4 14 1.8, 2.5, 3.3 & Adj (1.24 & up) 1500 mA ✔ ✔ 300 WEBENCH Tool TSSOP-16 

LM2653 4 14 Adj (1.2V & up) 1500 mA ✔ ✔ 300 Power good flag TSSOP-16 

LM2655 4 14 3.3 & Adj (1.23 & up) 2500 mA ✔ ✔ 300 — TSSOP-16 

LM2599 4.5 40 3.3 & Adj (1.23 & up) 3000 mA ✔ — 150 WEBENCH Tool TO263-7, TO220-7 

LM2650 4.5 18 Adj (1.25 & up) 3000 mA ✔ ✔ 90 to 300 Sync clock SO-24 

LM2673 8 40 3.3 & Adj (1.21 & up) 3000 mA — — 260 WEBENCH Tool TO263-7, LLP-14, TO220-7 

LM2679 8 40 3.3 & Adj (1.21 & up) 5000 mA — — 260 WEBENCH Tool TO263-7, LLP-14, TO220-7 

Synchronous buck controllers 

LM3475 2.7 10 Adj (0.8V & up) 1A to 3A ✔ — DC to 2000 — SOT23-5 

LM2743 1 16 Adj (0.6V & up) 1A to 20A ✔ ✔ 50 to 2000 Single controller TSSOP-14 

LM2647 5.5 28 Adj (0.6V & up) 1A to 20A ✔ ✔ 200 to 500 Dual controller TSSOP-28, LLP-28 

LM5642 4.5 36 Adj (1.25V & up) 1A to 20A ✔ ✔ 150 to 250 Dual controller TSSOP-28 

LM2633 4.5 30 Adj (0.9V & up) 1A to 20A ✔ ✔ 250 Dual + LDO TSSOP-48 

LM2645 4.5 30 Adj (1.25V & up) 1A to 20A ✔ ✔ 200, 300 Dual + LDO + 3.3V TSSOP-48 


LP3990 2 6 1.2, 1.5, 1.8, 2.5, 3.3 150 mA ✔ — — 0.47 µF C OUT SOT23-5, LLP-6, micro SMD-4 

LP2986 2.1 16 3.3 & Adj (1.24 & up) 200 mA ✔ — — Power good flag LLP-8, MSOP-8, SO-8 

LP2992 2.5 16 1.5, 1.8, 2.5, 3.0, 3.3 250 mA ✔ — — Power good flag SOT23-5, LLP-6 

LP3981 2.7 6 2.5, 3.3 300 mA ✔ — — Low noise LDO SO-8, LLP-6 

LP3982 2.5 6 1.8, 2.5, 3.0, 3.3 & Adj (1.25 & up) 300 mA ✔ — — Power good flag SO-8, LLP-8 

LM2937 4.75 26 2.5, 3.3 500 mA — — — Transient protection SOT223-4, TO263-3, TO220-3 

LP2989 2.1 16 1.8, 2.5, 3.3 500 mA ✔ — — Power good flag MSOP-8, SO-8, LLP-8 

LP8345 2.7 10 1.8, 2.5, 3.3 & Adj (1.25 & up) 500 mA — — — — TO252-3, LLP-6 

LP3874 2.5 7 1.2, 1.8, 2.5, 3.3 & Adj (1.2 & up) 800 mA ✔ — — Sense pin SOT223-5, TO263-5, TO220-5 

LP3875 2.5 7 1.2, 1.8, 2.5, 3.3 & Adj (1.2 & up) 1500 mA ✔ — — Sense pin SOT223-5, TO263-5, TO220-5 

22

Select voltage supervisors/power-on-reset ICs 

& application notes 

Select voltage supervisors/power-on-reset ICs 

Product 

ID 

Voltage rails 

supervised 

Reset flag 

active 

Reset timeout 

period 

Low-line 

output 

Manual 

reset 

Power 

fail comp 

Watchdog 

POR Packaging 

LM3704 2.35, 2.5, 2.8, 3.3, 5.0 1 Low 1.4, 28, 200, 1600 ms 2 ✔ ✔ ✔ — ✔ micro SMD-9, MSOP-10 

LM3705 2.5, 3.3, 5.0 1 High 1.4, 28, 200, 1600 ms 2 ✔ ✔ ✔ — ✔ micro SMD-9, MSOP-10 

LM3710 2.5, 3.3, 4.8, 5.0 1 Low 1.4, 28, 200, 1600 ms 2 ✔ ✔ ✔ ✔ ✔ micro SMD-9, MSOP-10 

LM3711 2.5, 3.3, 5.0 1 High 1.4, 28, 200, 1600 ms 2 ✔ ✔ ✔ ✔ ✔ micro SMD-9, MSOP-10 

LM3722/24 2.5, 3.3, 5.0 Low 190 ms — ✔ — — ✔ SOT23-5 

LM3723 2.5, 3.3, 5.0 High 190 ms — ✔ — — ✔ SOT23-5 

LP3470 2.8, 3.1, 3.3, 3.9, 4.3, 4.7, 5.0 1 Low Adj w/ external cap. — — — — ✔ SOT23-5 

LMC6953 3.3 and 5.0 (Dual) Low Adj w/ external cap. — ✔ — — ✔ SO-8 

LM8365 2.5, 3.0, 3.3, 5.0 Low Adj w/ external cap. — — — — ✔ SOT23-5 

1 

For custom reset threshold voltages between 2.2V and 5V in 10 mV increments, contact National Semiconductor. 

2 

Factory programmed options. Some of these options are available upon request. Please contact your National sales representative for more information. 

Select Altera application notes 

AN-74 Evaluating power for Altera devices 

AN-107 Using Altera devices in multiple voltage systems 

AN-355 Stratix II device system power considerations 

AN-358 Thermal management for 90 nm FPGAs 

To view or download these application notes, visit: 


Select National application notes 


AN-1148 Linear regulators: Theory of operation and compensation 

AN-1254 DDR-SDRAM termination simplified using a linear regulator 

Packaging technology 

AN-1028 Maximum power enhancement techniques for power packages 

AN-1187 Leadless leadframe package (LLP) 

AN-1201 LLP-8 thermal performance and design guidelines 

Plastic-misc Plastic package dimensional/thermal data 

Switching regulators and controllers 

AN-556 Introduction to power supplies 

AN-558 Introduction to power MOSFETs and their applications 

AN-643 EMI/RFI board design 

AN-1149 Layout guidelines for switching power supplies 

AN-1197 Selecting inductors for buck converters 

AN-1229 SIMPLE SWITCHER PCB layout guidelines 

AN-1246 Stresses in wide-input DC-DC converters 

Other 

AN-1200 Mixed signal testing using the IEEE 1149.4 STA400 

AN-1312 SCAN bridge (STA111/STA112) timing 

AN-1327 Simplified programming of Altera FPGAs using a SCANSTA111/112 SCAN chain mux 

23

Design tools 

Power Expert automated power solutions finder for Altera FPGAs and CPLDs 

Step 1. Choose Altera FPGA 

• Select the Altera FPGA you are using 

• The specific device’s power requirements are presented 

for your review. 

Step 2. Choose your operating conditions 

• Choose your operating conditions (i.e., input voltage, 

I/O voltage) 

• Using a slide bar, set the FPGA operating current within 

the allowable range — dissipated power is calculated for you. 

Step 3. Choose a National power solution 

• Choose the National solution desired — most efficient or more simple. 

• Review the National products that fit your design requirements 

and click on the links to view datasheets, design with WEBENCH 

tools (if available for the device), and download a sample 

reference design. 

To download this tool and view more information, visit: 


WEBENCH ® online design and prototyping environment 

Step 1. Select It 

• Input your design requirements 

• Choose a recommended part from a 

customized list 

Step 2. Design It 

• Adjust components and exercise 

operating values such as power 

dissipation, current flow, offset voltage, 

drift, and frequency response 

• Exchange parts to compare 

performance, size, and cost 

• Use recommended components or 

create a custom BOM 

Step 3. Analyze It 

• Stimulate your circuit and evaluate performance 

using electrical and thermal simulations 

• Overlay alternate circuits and compare results 

to get optimal performance 

Step 4. Build It 

• Request samples and purchase 

parts or demo boards 

• Receive your custom prototyping 

kit the next business day 

• Download your automatically 

generated CAD files, assembly 

details, test instructions, 

and complete performance 

characteristics — instantly! 

Step 5. Test It 

• Download your custom test 

vectors to verify your real board 

versus virtual results 

• Perform board-level tests 

using National Instruments’ 

SignalExpress software 

To use this tool and view more 

information, visit: 

webench.national.com 

24

Featured power management solutions 

Switching regulators 

LM2798, LM3352, LM2770 Inductorless switching regulators 

• 1.2, 1.5, 1.8, 2.5, 3.0 and 3.3V out 

• Step-down and/or step-up 

• Up to 250 mA I OUT 

• High efficiency (80%) 

• No inductor required, uses small ceramic caps 

• Always stable: no compensation required 

• High switching frequency 

• Ideal for high-efficiency CPLD power and batteryoperated 

devices 


V OUT = 1.5V, 1.8V, or 2.0V 

V IN = 2.6V to 5.5V 

I OUT up to 120 mA 

10 µF 

V IN 

C1+ 

V OUT 

C2+ 

10 µF 

1 µF 1 µF 

C1- LM2798 C2- 

EN 

BATOK 

POK 

GND 

LP385x/7x High-performance CMOS LDOs 

• Ultra-low dropout voltage (280 mV @ 1.5A, 

450 mV @ 3A max at 25°C) 

• Stable with 10 µF ceramic caps (LP385x) 

• Option for sense pin (LP3855/56) and error flag 

(LP3852/53) 

 

LP3853 Typical application diagram 

 

 

• Low ground-pin current (4 mA @ 3A) 

• On/off control 

• Over-temperature/over-current protection 

• Available in TO263-5, TO220-5, and SOT223-5 

packaging 

Output current Product ID V OUT options V OUT accuracy V IN range 

Single input rail (for V IN ≥ 2.5V) 

Dropout voltage 

full load (mV) 

Packaging 

800 mA LP3871/74 1.8, 2.5, 3.3, 5.0, Adj* 1.5% 2.5 to 7.0 300 TO263-5, TO220-5, SOT223-5 

1.5A LP3852/55 1.8, 2.5, 3.3, 5.0, Adj* 1.5% 2.5 to 7.0 280 TO263-5, TO220-5, SOT223-5 

1.5A LP3872/75 1.8, 2.5, 3.3, 5.0, Adj* 1.5% 2.5 to 7.0 450 TO263-5, TO220-5, SOT223-5 

3A LP3853/56 1.8, 2.5, 3.3, 5.0, Adj* 1.5% 2.5 to 7.0 450 TO263-5, TO220-5 

3A LP3873/76 1.8, 2.5, 3.3, 5.0, Adj* 1.5% 2.5 to 7.0 1000 TO263-5, TO220-5 

Dual input rail (for V IN ≥ 1.5V) 

800 mA LP3881 1.2, 1.5, 1.8, Adj 1.5% V OUT + V DO > 5.5 120 TO263-5, TO220-5 

800 mA LP3891 1.2, 1.5, 1.8, Adj 1.5% V OUT + V DO > 5.5 300 TO263-5, TO220-5 

1.5A LP3882 1.2, 1.5, 1.8, Adj 1.5% V OUT + V DO > 5.5 170 TO263-5, TO220-5 

1.5A LP3892 1.2, 1.5, 1.8, Adj 1.5% V OUT + V DO > 5.5 320 TO263-5, TO220-5 

3A LP3883 1.2, 1.5, 1.8 1.5% V OUT + V DO > 5.5 270 TO263-5, TO220-5 

3A LP3893 1.2, 1.5, 1.8 1.5% V OUT + V DO > 5.5 650 TO263-5, TO220-5 

*Adj available in LP3855/56/74/75/76 

25

National Semiconductor continually expands its product portfolio to offer the broadest range of 

power management and other analog solutions in the industry. For more information on National’s 

solutions for Altera FPGAs and CPLDs, visit us today at www.national.com/see/alterafpga 

Americas 

Email: new.feedback@nsc.com 

Phone: 1-800-272-9959 

Europe 

Fax: +49 (0) 180-530 85 86 

Email: europe.support@nsc.com 

Phone: 

Deutsch +49 (0) 69 9508 6208 

English +44 (0) 870 24 0 2171 

Français +33 (0) 1 41 91 87 90 

Asia Pacific 

Email: ap.support@nsc.com 

Japan 

Fax: 81-3-5639-7507 

Email: jpn.feedback@nsc.com 

Phone: 81-3-5639-7560 

Packaging 

LLP ® 

(Leadless leadframe) 

JA 40 to 60°C/W 

National’s LLP ® provides excellent power dissipation 

capability in a very small package footprint. Unlike 

conventional leaded plastic packages, the LLP contains 

pads on the bottom of the package for PCB mounting. 

micro SMD 

(small and large bump) 

JA 220 to 290°C/W 

MDIP 

(Molded dual-in-line package) 

JA 30 to 90°C/W 

MSOP 

(Mini 8-lead) 

JA 220°C/W 

PSOP-8 

JA 43°C/W 

SO 

(Small outline 

molded/ceramic) 

JA 100 to 190°C/W 

SOT-223 

(Power surface mount) 

JA 60 to 110°C/W 

SOT-23 

JA 120 to 290°C/W 

TO-220 

JA 45 to 65°C/W 

TO-252 

(DPAK) 

JA 60 to 90°C/W 

TO-263 

(Power surface mount) 

JA 35 to 60°C/W 

TSSOP 

JA 40 to 150 °C/W 

N a t i o n a l 

Semiconductor 

The Sight & Sound of Information 

© National Semiconductor Corporation, March 2005. National Semiconductor, , LLP, WEBENCH, LMH, and SIMPLE SWTICHER are registered trademarks of National Semiconductor. Altera, Stratix, 

Stratix II, Cyclone and MAX II are trademarks of Altera Corporation. Bluetooth is a registered trademark of Bluetooth SIG, Inc. and is used under license by National Semiconductor. 

Signal Express is a trademark of National Instruments. All rights reserved. 

570011-002

Power Management Design Guide for AlteraÂ® FPGAs and CPLDs ...

Create successful ePaper yourself

Delete template?

Save as template?