Power Management Design Guide for Altera® FPGAs and CPLDs ...
Power Management Design Guide for Altera® FPGAs and CPLDs ...
Power Management Design Guide for Altera® FPGAs and CPLDs ...
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<strong>Design</strong> considerations <strong>for</strong> powering <strong>FPGAs</strong> & <strong>CPLDs</strong><br />
Bulk capacitance<br />
In any power supply, the output capacitors are a vital<br />
element <strong>for</strong> adequate per<strong>for</strong>mance. They are used to<br />
control the output voltage ripple (ΔV OUT ) <strong>and</strong> to supply<br />
load current during fast load transients. Various types<br />
of capacitors may be used. However, the ceramic type<br />
often do not have the large capacitance needed to supply<br />
current <strong>for</strong> load transients, <strong>and</strong> tantalums tend to be more<br />
expensive than aluminum electrolytic.<br />
Adding bulk capacitance to the output of high-current<br />
switching supplies is always recommended <strong>and</strong> is also very<br />
important <strong>for</strong> adequate FPGA per<strong>for</strong>mance. Bulk capacitance<br />
helps provide current during start-up transients, thus<br />
supporting an adequate monotonic voltage rise in highcurrent<br />
power supplies. More in-depth recommendations<br />
on the use <strong>and</strong> benefits of bulk capacitance in FPGA<br />
power supplies are available in Altera’s application note<br />
AN-355 (see page 23 <strong>for</strong> download in<strong>for</strong>mation).<br />
Layout<br />
FPGA power design can involve very high currents (5A,<br />
10A, <strong>and</strong> 15A are common) flowing in the traces of the<br />
PCB. When these larger currents are present <strong>and</strong> change<br />
over time in a switching pattern with sharp edges, it is easy<br />
to realize that noise, induced voltages, <strong>and</strong> EMI may be<br />
present <strong>and</strong> may cause undesirable behavior in the power<br />
supply if proper care is not taken. This is why proper layout<br />
is critical in every switching regulator design. Rapidly<br />
switching currents associated with wiring inductance can<br />
also generate voltage transients which may cause additional<br />
problems. For minimal inductance <strong>and</strong> ground loops,<br />
the PCB traces conducting high current <strong>and</strong>/or switching<br />
wave<strong>for</strong>ms should be kept as short as possible.<br />
For best results, external components should be located as<br />
close to the switcher IC as possible, using ground-plane<br />
construction or single-point grounding. If open core<br />
inductors are used, special care must be taken as to the<br />
location <strong>and</strong> positioning of this type of inductor. Allowing<br />
the inductor flux to intersect sensitive feedback IC ground<br />
path <strong>and</strong> C OUT wiring can cause problems.<br />
When using a switching regulator or controller with an<br />
adjustable output, special care must be taken as to the<br />
location of the feedback resistors <strong>and</strong> the associated wiring.<br />
Physically locate both resistors near the IC <strong>and</strong> route the<br />
wiring away from the inductor, especially an open core<br />
type of inductor. Ferrite bobbin or stick inductors have<br />
magnetic lines of flux flowing through the air from one<br />
end of the bobbin to the other end. These magnetic lines<br />
of flux will induce a voltage into any wire or PC board<br />
copper trace that comes within the inductor’s magnetic field.<br />
The strength of the magnetic field, the orientation <strong>and</strong><br />
location of the PC copper trace to the magnetic field, <strong>and</strong><br />
the distance between the copper trace <strong>and</strong> the inductor<br />
determine the amount of voltage generated in the copper<br />
trace. For a deeper underst<strong>and</strong>ing of buck converters<br />
<strong>and</strong> PCB layout guidelines around them, see National’s<br />
application notes AN-1149 <strong>and</strong> AN-1229 (see page 23 <strong>for</strong><br />
download in<strong>for</strong>mation).<br />
Softstart<br />
As with most digital systems, <strong>FPGAs</strong> need their supply voltage<br />
to rise from zero to full voltage within a specified period of<br />
time. Altera <strong>FPGAs</strong> are very flexible <strong>and</strong> the requirements<br />
are not difficult to meet, but start-up timing still needs to<br />
be observed. For example, Stratix II <strong>FPGAs</strong> need V CCINT to<br />
rise in a window anywhere from 30 µs to 100 ms. To achieve<br />
that controlled rise time, softstart in the power supply must<br />
be used. Most switching regulators <strong>and</strong> controllers already<br />
have softstart incorporated, either internally fixed or externally<br />
programmable. When user programmable, a softstart pin (SS)<br />
is available <strong>and</strong> softstart timing is typically adjusted by placing<br />
a small capacitor between that pin <strong>and</strong> ground. Depending on<br />
the capacitor value, the softstart time will change.<br />
In<strong>for</strong>mation on which capacitor values to use <strong>and</strong> how to<br />
calculate the needed value to achieve a particular ramp-up<br />
time is described on each switching regulator’s datasheet.<br />
For linear regulators where softstart is not typically an<br />
internally implemented function, an external pass device<br />
is used along with a resistor <strong>and</strong> a capacitor to achieve this<br />
same effect.<br />
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