Power Management Design Guide for AlteraÂ® FPGAs and CPLDs ...

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National power solutions for Stratix II FPGAs Stratix II FPGAs Stratix II FPGAs are Altera’s highest-density, highestperformance devices. Built on a 90-nm process technology, they incorporate a new logic structure that on average delivers 50% faster core performance with more than twice the logic capacity and costs 40% less than first-generation Stratix devices. Support is implemented for internal clock frequency rates of up to 500 MHz and typical design performance at over 250 MHz. Based on a 1.2V SRAM process, Stratix II devices are available in densities ranging from 15,600 to 179,400 equivalent logic elements (LEs) and up to 9 Mbits of on-chip RAM. Stratix II devices offer up to 384 (18-bit x 18-bit) embedded multipliers in highly optimized digital signal processing (DSP) blocks and source-synchronous differential signaling with dedicated dynamic phase alignment (DPA) circuitry operating at up to 1 Gbps. The core of these FPGAs needs to be powered from a 1.20V source. This voltage (V CCINT ) should always be within 1.15V and 1.25V during regular operation. Core current consumption (I CCINT ) depends upon utilization of the part (such as clock speed and internal elements used). The I/O banks of this FPGA family are compatible with multiple standards, thus the supply voltage (V CCIO ) can either be 1.5V, 1.8V, 2.5V or 3.3V for one or more banks. Current consumption for the I/Os also depends upon the utilization of these elements, however for all I/O banks operating together, the max I CCIO for the Stratix II FGPA is 10A (independent of the V CCIO voltage used). Another power management consideration that needs to be addressed is the monotonic rise of V CCINT . This consideration is critical for the correct operation of the FPGA. While many power supplies take this requirement into consideration, it is recommended to further support this requirement by the use of adequate bulk capacitance in the power supply. LM2743 Low-voltage synchronous buck controller • Highly efficient 2A to 25A solution in SMD • Input voltage from 1V to 16V • Adjustable output voltage as low as 0.6V • Power-good flag and output enable • Output under-voltage and over-voltage flag • 1.5% reference accuracy over temperature • Current limit without sense resistor • Programmable softstart • Switching frequency from 50 kHz to 2 MHz • Available in small TSSOP-14 packaging LM2743 Typical application diagram Ideal for operation from 3.3V or 5V supplies in FPGA, DSP, and other high-current core regulator applications 4
Stratix II FPGAs Stratix II power requirements summary EP2S15 EP2S30 EP2S60 EP2S90 EP2S130 EP2S180 V CCINT (V core) 1.20V 1.20V 1.20V 1.20V 1.20V 1.20V I CCINT max (I core) Dynamic power consumption is design dependent. For accurate estimates, use Altera’s suite of PowerPlay power estimation tools. For more information: www.altera.com/support/devices/estimator/pow-powerplay.html V CCIO options (V I/O) 3.3, 2.5, 1.8, 1.5V 3.3, 2.5, 1.8, 1.5V 3.3, 2.5, 1.8, 1.5V 3.3, 2.5, 1.8, 1.5V 3.3, 2.5, 1.8, 1.5V 3.3, 2.5, 1.8, 1.5V National power solutions for Stratix II FPGAs V IN = 3.3V V IN = 5V V IN = 12V 5 V CCINT V CCINT = 1.2V I CCINT < 1000 mA (LDO) LP3875-Adj Not applicable 1 Not applicable 1 I CCINT < 1000 mA (SW) LM2734 LM2734 LM2734 I CCINT < 3A LM3475 LM3475 LM2673-Adj I CCINT < 5A LM2743 LM2743 LM2679-Adj 2 or LM2743 3 I CCINT > 6A LM2743 LM2743 or 1 / 2 LM2657 4 LM2743 or 1 / 2 LM2657 4 V CCIO V CCIO = 1.5V V CCIO = 1.8V V CCIO = 2.5V V CCIO = 3.3V I CCIO < 500 mA (LDO) LP3874-Adj LP3874-Adj Not applicable 1 I CCIO < 500 mA (SW) LM3671-1.5 LM3671-1.5 LM2736 I CCIO < 1000 mA (LDO) LP3875-Adj Not applicable 1 Not applicable 1 I CCIO < 1000 mA (SW) LM2734 LM2734 LM2734 I CCIO < 3A LM3475 LM2599-Adj 2 or LM2650-Adj 3 LM2673-Adj 2 or LM2650-Adj 3 I CCIO < 5A LM2743 LM2743 LM2679-Adj I CCIO > 6A LM2743 LM2743 or 1 / 2 LM2657 4 LM2743 or 1 / 2 LM2657 4 I CCIO < 500 mA (LDO) LP3874-1.8 LP3874-1.8 Not applicable 1 I CCIO < 500 mA (SW) LM3671-1.8 LM3671-1.8 LM2736 I CCIO < 1000 mA (LDO) LP3875-1.8 Not applicable 1 Not applicable 1 I CCIO < 1000 mA (SW) LM2734 LM2734 LM2734 I CCIO < 3A LM3475 LM2599-Adj 2 or LM2650-Adj 3 LM2673-Adj 2 or LM2650-Adj 3 I CCIO < 5A LM2743 LM2743 LM2679-Adj I CCIO > 6A LM2743 LM2743 or 1 / 2 LM2657 4 LM2743 or 1 / 2 LM2657 4 I CCIO < 500 mA (LDO) LP3874-2.5 LP3874-2.5 Not applicable 1 I CCIO < 500 mA (SW) LM3671-Adj LM3671-Adj LM2736 I CCIO < 1000 mA (LDO) LP3875-2.5 LP3875-2.5 Not applicable 1 I CCIO < 1000 mA (SW) LM2734 LM2734 LM2734 I CCIO < 3A LM3475 LM2599-Adj 2 or LM2650-Adj 3 LM2673-Adj 2 or LM2650-Adj 3 I CCIO < 5A LM2743 LM2743 LM2679-Adj I CCIO > 6A LM2743 LM2743 or 1 / 2 LM2657 4 LM2743 or 1 / 2 LM2657 4 I CCIO < 500 mA (LDO) — LP3874-3.3 Not applicable 1 I CCIO < 500 mA (SW) — LM3671-Adj LM2736 I CCIO < 1000 mA (LDO) — LP3875-3.3 Not applicable 1 I CCIO < 1000 mA (SW) — LM2734 LM2734 I CCIO < 3A — LM2599-3.3 2 or LM2650-Adj 3 LM2673-3.3 2 or LM2650-Adj 3 I CCIO < 5A — LM2743 LM2679-3.3 I CCIO > 6A — LM2743 or 1 / 2 LM2657 4 LM2743 or 1 / 2 LM2657 4 V CCPD V CCPD = 3.3V I CCPD < 300 mA (LDO) — LP3981-3.3 Not applicable 1 I CCPD < 300 mA (SW) — LM3670-3.3 LM2736 1 LDO option not applicable due to thermal constraints (heat dissipation) for the given operating conditions. 2 Buck regulator. Good efficiency, simple implementation, with WEBENCH design tools available. 3 Synchronous buck converter. Maximum efficiency, no external diode required. 4 One half of a dual converter, such as the LM2657, can be used to power V CCINT while the other half can be used to power V CCIO . 5 These solutions can be used with input voltages from 8V to 14V. 5
Page 1 and 2: Power Management Design Guide for A
Page 3 and 4: Contents Featured power products fo
Page 5: Selecting the best power architectu
Page 9 and 10: Stratix FPGAs Stratix power require
Page 11 and 12: Cyclone FPGAs Cyclone power require
Page 13 and 14: MAX II CPLDs MAX II power requireme
Page 15 and 16: Monotonic voltage rise Although not
Page 17 and 18: Stratix II & Stratix FPGAs Stratix
Page 19 and 20: Stratix II & Stratix FPGAs Stratix
Page 21 and 22: MAX II CPLDs MAX II Complete Pow
Page 23 and 24: High-speed data conversion ICs Prod
Page 25 and 26: Select voltage supervisors/power-on
Page 27 and 28: Featured power management solutions

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