Power Management Design Guide for Altera® FPGAs and CPLDs ...

National power solutions for MAX II CPLDs
MAX II CPLDs
The MAX II CPLD family is a non-volatile, instant-on
programmable logic family with a new CPLD architecture,
which allows significant power and density enhancements
from previous MAX devices. Based on a 0.18-µm Flash
process, the MAX II devices offer densities ranging from 240
to 2,210 logic elements (LEs) and up to 272 user I/O pins.
The core of these CPLDs (V CCINT ) needs to be powered from
a 1.8V source. The non-G versions of MAX II devices have
an internal voltage regulator and the V CCINT pin can accept
either 3.3V or 2.5V. This internal regulator steps down
the voltage to the needed 1.8V. On the G-version MAX II
CPLDs, the internal regulator is bypassed and V CCINT needs
to be only 1.8V. Core current consumption (I CCINT ) depends
upon utilization of the part (such as clock speed and internal
elements used), but typical values range from 30 mA to 75
mA with maximum values in the 75 mA to 400 mA range.
Typically, operating core current (I CCINT ) for MAX II devices
National power solutions
for MAX II CPLDs
will be 10 mA less in the 1.8V G versions. The I/O current
(I CCIO ) also depends upon the device utilization, with typical
values in the 100 mA to 200 mA range. Maximum values can
reach 225 mA per bank or 900 mA total for up to four banks.
To calculate the most accurate power consumption values
needed by your specific design, we recommend using
Altera’s Power Calculator tool, available online. A good rule
of thumb is to choose a V CCINT power supply whose I OUT
(I CCINT ) capability is within the I CCINT inrush and I CCINT
maximum values. As opposed to FPGAs, these CPLDs do
not have specific requirements for monotonic voltage rise or
V CCINT rise times. Since MAX II CPLDs consume low power,
the use of LDOs and inductorless switching regulators is
recommended. For LDOs, it is advised to check the thermal
dissipation capability of the part based on the package and
the operating conditions. It is not enough to check V IN , V OUT
and I OUT alone for selecting LDOs. The LDOs recommended
in the following tables address thermal dissipation capabilities.
V IN = 3.3V V IN = 5V V IN = 12V
V CCINT
V CCINT = 1.8V
V CCINT = 2.5V
V CCINT = 3.3V
I CCIO < 100 mA (LDO) LP3990-1.8 LP3990-1.8 LP2992-1.8 5
I CCIO < 100 mA (SW) LM2798-1.8 4 LM2798-1.8 4 LM2736
I CCIO < 150 mA (LDO) LP3990-1.8 LP3982-1.8 LP2992-1.8 5
I CCIO < 150 mA (SW) LM3670-1.8 3 LM3670-1.8 3 LM2736
I CCIO < 200 mA (LDO) LP3982-1.8 LP3982-1.8 Not applicable 1
I CCIO < 200 mA (SW) LM3670-1.8 3 LM3670-1.8 3 LM2736
I CCIO < 300 mA (LDO) LP3982-1.8 LP8345-1.8 Not applicable 1
I CCIO < 300 mA (SW) LM3670-1.8 3 LM3670-1.8 3 LM2736
I CCIO < 500 mA (LDO) LP8345-1.8 LP3874-1.8 Not applicable 1
I CCIO < 500 mA (SW) LM3671-1.8 3 LM3671-1.8 3 LM2736
I CCIO < 100 mA (LDO) LP3990-2.5 LP3990-2.5 LM2937-2.5 or LP2992-2.5 5
I CCIO < 100 mA (SW) LM3352-2.5 4 LM3352-2.5 4 LM2736
I CCIO < 150 mA (LDO) LP3990-2.5 LP3982-2.5 LM2937-2.5 or LP2992-2.5 5
I CCIO < 150 mA (SW) LM3352-2.5 4 LM3352-2.5 4 LM2736
I CCIO < 200 mA (LDO) LP3982-2.5 LP3982-2.5 LM2937-2.5 or LP2992-2.5 5
I CCIO < 200 mA (SW) LM3352-2.5 4 LM3352-2.5 4 LM2736
I CCIO < 300 mA (LDO) LP3982-2.5 LP8345-2.5 Not applicable 1
I CCIO < 300 mA (SW) LM3670-2.5 3 LM3670-2.5 3 LM2736
I CCIO < 500 mA (LDO) LP2989-2.5 LP3874-2.5 Not applicable 1
I CCIO < 500 mA (SW) LM3671-Adj 3 LM3671-Adj 3 LM2736
I CCIO < 100 mA (LDO) — LP3990-3.3 LM2937-3.3 or LP2986-3.3 5
I CCIO < 100 mA (SW) — LM3352-3.3 4 LM2736
I CCIO < 150 mA (LDO) — LP3990-3.3 LM2937-3.3 or LP2986-3.3 5
I CCIO < 150 mA (SW) — LM3352-3.3 4 LM2736
I CCIO < 200 mA (LDO) — LP3982-3.3 LM2937-3.3 or LP2986-3.3 5
I CCIO < 200 mA (SW) — LM3352-3.3 4 LM2736
I CCIO < 300 mA (LDO) — LP3982-3.3 Not applicable 1
I CCIO < 300 mA (SW) — LM3670-3.3 3 LM2736
I CCIO < 500 mA (LDO) — LP8345-3.3 Not applicable 1
I CCIO < 500 mA (SW) — LM3671-Adj 3 LM2736
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