Power Management Design Guide for Altera® FPGAs and CPLDs ...

National power solutions for Stratix FPGAs
Stratix FPGAs
The Stratix FPGA family is optimized to address the
challenges of high-bandwidth systems. Stratix devices offer
very high core performance, memory capacity, architectural
efficiencies, and time-to-market advantages. Stratix devices
offer dedicated functionality for clock management and
digital signal processing (DSP) applications, as well as
support for differential and single-ended I/O standards.
In addition, Stratix devices offer on-chip termination and
remote system upgrade capabilities.
Based on a 1.5V, 0.13-µm, all-layer copper SRAM process,
Stratix devices are available in densities ranging from
10,570 to 79,040 logic elements (LEs) and up to 7 Mbits
of RAM. Stratix devices offer up to 22 DSP blocks with
up to 176 (9-bit x 9-bit) embedded multipliers, optimized
complex applications that require high data throughput.
The core of these FPGAs needs to be powered from a 1.5V
source. Core current consumption (I CCINT ) depends upon
utilization of the part (such as clock speed and internal
elements used), but maximum values range from 1.5A to
10A (approx.) depending on the specific Stratix device
used. To calculate the most accurate power consumption
values needed by a specific design, use Altera’s Power
Calculator tool (see www.national.com/see/alterafpga). As
a general rule, choose a V CCINT power supply whose I OUT
(I CCINT ) capability is within the I CCINT inrush and I CCINT
maximum values given in this guide for the specific Altera
device used.
Another power management consideration that needs
to be addressed is the monotonic rise of V CCINT . This
consideration is critical for the correct operation of the
FPGA. While many power supplies take this requirement
into consideration, it is recommended to further support
this requirement by the use of adequate bulk capacitance
in the power supply.
LM2647 Dual synchronous buck controller
• Input voltage range from 5.5V to 28V
• Synchronous dual-channel interleaved
switching
• PWM or pulse-skip modes
• Low-side MOSFET current sensing
• Adjustable output voltage down to 0.6V
• Power-good flag and chip enable
• Under-voltage lockout hysteresis
• Over-voltage/under-voltage protection
• Softstart and soft-shutdown
• Switching frequency adjustable from
200 kHz to 500 kHz
• Available in TSSOP-28 and tiny,
thermally enhanced LLP-28 packaging
LM2647 Efficiency curve
Ideal for powering high-current V CCINT and V CCIO FPGAs from the
same switching controller
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