Power Management Design Guide for Altera® FPGAs and CPLDs ...

Reference designs
Stratix II & Stratix FPGAs
Stratix II V CCINT Power Supply Reference Design
(5V in, 1.20V out @ 16A)
This third LM2743-based V CCINT reference design features
a high-current I CCINT output with an up to 16A capability
to ideally power the EP2S180 and the EP2S130 Stratix II
FPGAs. It can also be used to power the EP1S80 Stratix
device, making the V CCINT 1.5V. As previously described in
the “Powering FPGA Design Considerations” section, it is
highly recommended to place proper bulk capacitance in
the output of the power supply when large I CCINT current
is involved. This is needed for the adequate performance
of the FPGA during load transient conditions and also to
help in proper start-up of the device during power up.
Stratix II/Stratix V CCIO 3A to 10A Power Supply Reference Design
(5V in, 1.8V out @ 10A)
The I/O banks in FPGAs can be powered at different
V CCIO voltages depending on the I/O standard at which
they will be used. Different I/O banks in the same FPGA
may be powered with different V CCIO voltages to work on
different I/O standards simultaneously.
The present LM2743-based design shows a high-current
power supply to power V CCIO at a typical 1.8V and has an
I OUT capability of up to 10A. Such high current is needed
by Stratix II or Stratix FPGAs when all banks (up to 8) are
fully utilized and powered from the same V CCIO . However,
this same power supply is adequate for powering I/O banks
that require current (I CCIO ) anywhere from 3A to 10A.
For additional information on these reference designs,
such as complete bills of material, test waveforms, and
performance reports, visit:
www.national.com/see/alterafpga
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