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Efficient Model for OFDM based IEEE 802.11 Receiver with Autocorrelation technique And… V. SIMULATION RESULTS OF THE PROPOSED MODELS The proposed model of both Autocorrelator and CORDIC algorithm have been coded in Verilog HDL, synthesized using Xilinx ISE 9.2i which also specifies the number of hardware required. Table I shows the hardware usage of the Autocorrelator. 5.1 Results of Autocorrelator block Figure 10. RTL Schematic of Autocorrelator The RTL schematic of proposed autocorrelator block is shown in fig 9. The proposed autocorrelator block is designed using various units like Adders, Subtractors, RAM, Flipflops, Multipliers. The main aim of autocorrelator block is done by the adder and subtractor unit. Adder and subtractor unit takes care of correlation process. RAM is used for storage purpose. It is used for storing both input sample and the delayed version of itself. TABLE I: HARDWARE USAGE OF AUTOCORRELATOR LOGIC UNIT NUMBER REQUIRED RAM 2 Multiplier 1 Adder/Subtractor 2 Counter 2 Accumulator 1 Register 2 Comparator 1 The maximum period and the maximum frequency of the proposed design is 21.792 ns and 45.888 MHz. The delay which is obtained in the proposed model is 10.896 ns and also the offset of the model is 15.492 ns. TABLE II: RESOURCE USAGE OF AUTOCORRELATOR LOGIC ELEMENTS UTILISED AVAILABLE Number of slice flipflops 64 1920 Number of 4 input LUTs 366 1920 Number of occupied slices 210 960 Total number of 4 input LUTs 387 1920 Number of bonded IOBs 43 66 Number of BUFGMUXs 1 24 Number of multiplier 1 4 Average fanouts of nonclock nets 5.43 - www.<strong>ijcer</strong>online.com ||May ||2013|| Page 95
Efficient Model for OFDM based IEEE 802.11 Receiver with Autocorrelation technique And… 5.2 Results of CORDIC Algorithm Figure 11. RTL schematic of CORDIC Algorithm The fig 10 shows the RTL Schematic of CORDIC Algorithm. This model consists of eight iterator blocks, adders/subtractors, comparators, multipliers and logic shifters. Each iterator block sequentially provides the output. The output of previous iterator block is taken as the input of next iterator block and process goes on sequentially like this upto eight iterations. TABLE III: HARDWARE USAGE OF AUTOCORRELATOR HARDWARE NUMBER REQUIRED Multiplier 4 Adder/Subtractor 32 Comparators 52 Logic shifters 40 IO buffer 48 IBUF 16 OBUF 32 IOs 49 The delay for the proposed CORDIC Algorithm is 66.321ns. The total memory usage which obtained in this model is 297012Kilo bytes. The total real time to Xst completion is 31s. The total CPU time to Xst completion is 31.24 s. TABLE IV: RESOURCE USAGE OF CORDIC ALGORITHM LOGIC ELEMENTS USED AVAILABLE Number of slice flipflops 542 960 Number of 4 input LUTs 1031 1920 Number of bonded IOBs 48 66 Number of multiplier 4 4 www.<strong>ijcer</strong>online.com ||May ||2013|| Page 96
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