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Area and Speed wise superior Vedic multiplier for FPGA based arithmetic circuits He organized and classified the whole of Vedic Mathematics into 16 formulae or also called as sutras. These formulae form the backbone of Vedic mathematics. Great amount of research has been done all these years to implement algorithms of Vedic mathematics on digital processors. It has been observed that due to coherence and symmetry in these algorithms it can have a regular silicon layout and consume less area along with lower power consumption. VI. URDHAVA TIRYAKBHYAM METHOD Urdhava Tiryakbhyam [2] is a Sanskrit word which means vertically and crosswire in English. The method is a general multiplication formula applicable to all cases of multiplication. It is based on a novel concept through which all partial products are generated concurrently. Fig. 2 demonstrates a 4 x 4 binary multiplication using this method. The method can be generalized for any N x N bit multiplication. This type of multiplier is independent of the clock frequency of the processor because the partial products and their sums are calculated in parallel. The net advantage is that it reduces the need of microprocessors to operate at increasingly higher clock frequencies. As the operating frequency of a processor increases the number of switching instances also increases. This results in more power consumption and also dissipation in the form of heat which results in higher device operating temperatures. Another advantage of Urdhva Tiryakbhyam multiplier is its scalability. The processing power can easily be increased by increasing the input and output data bus widths since it has a regular structure. Due to its regular structure, it can be easily layout in a silicon chip and also consumes optimum area. As the number of input bits increase, gate delay and area increase very slowly as compared to other multipliers. Therefore Urdhava Tiryakbhyam multiplier is time, space and power efficient. The line diagram in fig. 2 illustrates the algorithm for multiplying two 4-bit binary numbers a3a2a1a0 and b3b2b1b0. The procedure is divided into 7 steps and each step generates partial products. Initially as shown in step 1 of fig. 2, the least significant bit (LSB) of the multiplier is multiplied with least significant bit of the multiplicand (vertical multiplication). This result forms the LSB of the product. In step 2 next higher bit of the multiplier is multiplied with the LSB of the multiplicand and the LSB of the multiplier is multiplied with the next higher bit of the multiplicand (crosswire multiplication). These two partial products are added and the LSB of the sum is the next higher bit of the final product and the remaining bits are carried to the next step. For example, if in some intermediate step, we get the result as 1101, then 1 will act as the result bit(referred as rn) and 110 as the carry (referred as cn). Therefore cn may be a multi-bit number. Similarly other steps are carried out as indicated by the line diagram. The important feature is that all the partial products and their sums for every step can be calculated in parallel. Step 1 Step 2 Step3 Step4 Step 5 Step6 Step7 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 Fig. 2 Multiplication of two 4 bit numbers using Urdhava Tiryakbhyam method VII. FPGA ARCHITECTURE: Field-Programmable Gate Arrays (FPGAs) have become one of the key digital circuit implementation media over the last decade. A crucial part of their creation lies in their architecture, which governs the nature of their programmable logic functionality and their programmable inter-connect. FPGA architecture has a dramatic effect on the quality of the final device‟s speed performance, area efficiency, and power consumption. Field-Programmable Gate Arrays (FPGAs) are prefabricated silicon devices that can be electrically programmed to become almost any kind of digital circuit or system. FPGAs, as illustrated in Figure 3, consist of an array of programmable logic blocks of potentially different types, including general logic, memory and multiplier blocks, surrounded by a programmable routing fabric that allows blocks to be programmable interconnected. The array is surrounded by programmable input/output blocks, labeled I/O in the figure that connect the chip to the outside world. The “programmable” term in FPGA indicates an ability to program a function into the chip after silicon fabrication is complete. This customization is made possible by the programming technology, which is a method that can cause a change in the behavior of the pre-fabricated chip after fabrication, in the “field,” where system users create designs, www.<strong>ijcer</strong>online.com ||May ||2013|| Page 47
Area and Speed wise superior Vedic multiplier for FPGA based arithmetic circuits Fig.3: Basic FPGA structure. VIII. CHIP SCOPE RESULTS Here two 8- bit numbers are given to our vedic multiplier. The intermediate results from the 8-bit ripple carry adders, 4X4 vedic multiplier are used and we can observe the outputs of Vedic multiplier for variable length inputs by using Chipscope-VIO. These results for various inputs are verified using normal calculator. Data inputs given to vedic multiplier using Chipscope-VIO are as follows; Figure 5.3: Data inputs given to vedic multiplier using Chipscope-VIO ‣ Here we are giving the variable length inputs in runtime using Chipscope-VIO ‣ We can give desired inputs to Vedic multiplier at runtime are shown above. www.<strong>ijcer</strong>online.com ||May ||2013|| Page 48
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