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Efficient Model for OFDM based IEEE 802.11 Receiver with Autocorrelation technique And…<br />
VI. CONCLUSION<br />
The Proposed model concludes that the performance of the WLAN receiver has been enhanced by<br />
means of Autocorrelator and CORDIC Algorithm.<br />
Autocorrelator can perform synchronization for frame ,time and frequency. It has been also proved<br />
that Autocorrelation is suitable for synchronization. After a careful analysis of competing algorithms, it is<br />
decided that the best choice for time synchronization is to use the basic Auto-Correlation estimator. To get more<br />
accuracy for estimating the frequency offsets, CORDIC algorithm is used. It is used for estimating the carrier<br />
frequency offsets as well as compensating those frequencies by estimating the phase of the maximum<br />
correlating signal. It is more advantageous to greatly reduces the delay while using the multiplier hardware. In<br />
previous methods for estimating the offsets, eventhough it achieves better result it lack accuracy. But in the<br />
proposed model, the given sample is serially iterated in order to achieve the bit of accuracy. It also achieves<br />
minimum resource utilization.The proposed model also proved that the utility of devices is lesser than the other<br />
existing model. In the end, the proposed design consumed an relatively low quantity of hardware resources,<br />
gives less delay and produced excellent results for packet detection, frequency offset estimation, and time,<br />
frequency synchronization.<br />
VII. FUTURE WORK<br />
By getting the better results, it is also decided that the quantized 64 sample cross correlator, in<br />
conjunction with the maximum detector, it would be used for fine time synchronization. On analysis, it is<br />
obtained that the fast pipelined CORDIC architecture drastically increases area and power by increasing number<br />
of iterations and number of cells usage. Thus the algorithm is greatly enhanced in future use. This design can<br />
also be implemented in FPGA or ASIC to achieve the spectral efficiency in OFDM WLAN reciever. The<br />
minimization of the power difference or maximizing the SINR approaches could be considered to optimize the<br />
compensation process such that the system performance is improved. From the architectural point of view where<br />
the iterative process adds more challenge to the design of the synchronization unit. Furthermore, the timing and<br />
frequency synchronization architecture unit could be evaluated in a testbed OFDM system.<br />
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