Amplifier and Data Converter Selection Guide (Rev. B

58 ADCs by Architecture➔SAR ADCsSuccessive-approximation register (SAR)converters are frequently the architecture ofchoice for medium-to-high-resolutionapplications with medium sampling rates.SAR ADCs range in resolution from 8- to18-bits with speeds typically less than10MSPS. They provide low powerconsumption and a small form factor.A SAR converter operates on the same principleas a balance scale. On the scale, an unknownweight is placed on one side of the balancepoint, while known weights are placed on theother side and rejected or kept until the twosides are perfectly balanced. The unknownweight can then be measured by totaling upthe kept, known weights. In the SAR converter,the input signal is the unknown weight, whichis sampled and held. This voltage is thencompared to successive known voltages, andthe results are output by the converter. Unlikethe weigh scale, conversion occurs veryquickly through the use of charge redistributiontechniques.Because the SAR ADC samples the input signaland holds the sampled value until conversion iscomplete, this architecture does not make anyassumptions about the nature of the inputsignal, and the signal therefore does not needto be continuous. This makes the SARarchitecture ideal for applications where amultiplexer may be used prior to theconverter, or for applications where theconverter may only need to make ameasurement once every few seconds, or forapplications where a “fast” measurement isrequired. The conversion time remains thesame in all cases, and has little sample-toconversionlatency compared to a pipeline ordelta-sigma converter. SAR converters areideal for real-time applications such asindustrial control, motor control, powermanagement, portable/battery-poweredinstruments, PDAs, test equipment anddata/signal acquisition.Technical InformationModern SAR ADCs use a sample capacitorthat is charged to the voltage of the inputsignal. Due to the ADC's input capacitance,input impedance, and external circuitry, asettling time will be required for the samplecapacitor's voltage to match the measuredinput voltage.Minimizing the external circuitry's sourceimpedance is one way to minimize thissettling time, assuring that the input signal isaccurately acquired within the ADC’s acquisitiontime. A more troublesome design constraint,however, is the dynamic load that the SARADC's input presents to the driving circuitry.The op amp driver to the ADC input must beable to handle this dynamic load and settleto the desired accuracy within the requiredacquisition time.The SAR ADC's reference input circuitry presentsa similar load to the reference voltage. Whilethe reference voltage is supposed to be a verystable DC voltage, the dynamic load that theADC's reference input presents makes achievingREFCDACSARthis goal somewhat difficult. Thus, buffercircuitry is required for the referencevoltage, and the op amp used for this hassimilar requirements as that used for drivingthe ADC input; in fact, the requirements onthe op amp may be even higher than for theinput signal as the reference input must besettled within one clock cycle. Some convertershave this reference buffer amplifier built in.Buffering these inputs using op amps with alow, wideband output impedance is the bestway to preserve accuracy with theseconverters.To help facilitate the selection process,an interactive online data converterparametric search engine is available atdataconverter.ti.com with links to alldata converter specifications.In a SAR ADC, the bits are decided by a single high-speed, high-accuracycomparator bit by bit, from the MSB down to the LSB. This is done bycomparing the analog input with a DAC whose output is updated bypreviously decided bits and successively approximates the analog input.Serial InterfaceSERIALDCLOCS/SHAmplifier and Data Converter Selection Guide Texas Instruments 3Q 2007