Amplifier and Data Converter Selection Guide (Rev. B

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58 ADCs by Architecture➔SAR ADCsSuccessive-approximation register (SAR)converters are frequently the architecture ofchoice for medium-to-high-resolutionapplications with medium sampling rates.SAR ADCs range in resolution from 8- to18-bits with speeds typically less than10MSPS. They provide low powerconsumption and a small form factor.A SAR converter operates on the same principleas a balance scale. On the scale, an unknownweight is placed on one side of the balancepoint, while known weights are placed on theother side and rejected or kept until the twosides are perfectly balanced. The unknownweight can then be measured by totaling upthe kept, known weights. In the SAR converter,the input signal is the unknown weight, whichis sampled and held. This voltage is thencompared to successive known voltages, andthe results are output by the converter. Unlikethe weigh scale, conversion occurs veryquickly through the use of charge redistributiontechniques.Because the SAR ADC samples the input signaland holds the sampled value until conversion iscomplete, this architecture does not make anyassumptions about the nature of the inputsignal, and the signal therefore does not needto be continuous. This makes the SARarchitecture ideal for applications where amultiplexer may be used prior to theconverter, or for applications where theconverter may only need to make ameasurement once every few seconds, or forapplications where a “fast” measurement isrequired. The conversion time remains thesame in all cases, and has little sample-toconversionlatency compared to a pipeline ordelta-sigma converter. SAR converters areideal for real-time applications such asindustrial control, motor control, powermanagement, portable/battery-poweredinstruments, PDAs, test equipment anddata/signal acquisition.Technical InformationModern SAR ADCs use a sample capacitorthat is charged to the voltage of the inputsignal. Due to the ADC's input capacitance,input impedance, and external circuitry, asettling time will be required for the samplecapacitor's voltage to match the measuredinput voltage.Minimizing the external circuitry's sourceimpedance is one way to minimize thissettling time, assuring that the input signal isaccurately acquired within the ADC’s acquisitiontime. A more troublesome design constraint,however, is the dynamic load that the SARADC's input presents to the driving circuitry.The op amp driver to the ADC input must beable to handle this dynamic load and settleto the desired accuracy within the requiredacquisition time.The SAR ADC's reference input circuitry presentsa similar load to the reference voltage. Whilethe reference voltage is supposed to be a verystable DC voltage, the dynamic load that theADC's reference input presents makes achievingREFCDACSARthis goal somewhat difficult. Thus, buffercircuitry is required for the referencevoltage, and the op amp used for this hassimilar requirements as that used for drivingthe ADC input; in fact, the requirements onthe op amp may be even higher than for theinput signal as the reference input must besettled within one clock cycle. Some convertershave this reference buffer amplifier built in.Buffering these inputs using op amps with alow, wideband output impedance is the bestway to preserve accuracy with theseconverters.To help facilitate the selection process,an interactive online data converterparametric search engine is available atdataconverter.ti.com with links to alldata converter specifications.In a SAR ADC, the bits are decided by a single high-speed, high-accuracycomparator bit by bit, from the MSB down to the LSB. This is done bycomparing the analog input with a DAC whose output is updated bypreviously decided bits and successively approximates the analog input.Serial InterfaceSERIALDCLOCS/SHAmplifier and Data Converter Selection Guide Texas Instruments 3Q 2007
ADCs by ArchitectureSAR ADCs59➔12- and 16-Bit, ±10V Input, Single-Supply Family of SAR ADCsADS8504, ADS8505, ADS8506*, ADS8507, ADS8508, ADS8509, ADS8513*Get samples, datasheets, and evaluation modules at:www.ti.com/sc/device/PARTnumber (Replace PARTnumber with ADS8504, ADS8505, ADS8506, ADS8507, ADS8508, ADS8509 or ADS8513)Key Features• Resolution:• 12-bits (ADS8504/06/08)• 16-bits (ADS8505/07/09/13)• Sample rate: 250kSPS• Input ranges: up to ±10V (ADS8504/05)4V, 5V, 10V, ±3.3V, ±5V, ±10V (ADS8506/07/08/09/13)• THD: –98dB with 20kHz input• Single supply: 5V• Low power: 70mW (typ) at 250kSPS• Internal/external reference• Full parallel data output (ADS8504/05/06);SPI-compatible serial output with daisy-chain(TAG) feature (ADS8507/08/09/13)• Packaging: SOIC-28, SSOP-28 and SO-20Applications• Industrial process control• Data acquisition systems• Medical equipment• Instrumentation• Digital signal processingThe ADS850x family of devices are SAR ADCs complete with S/H, reference, clock, interface formicroprocessor use and 3-state output drivers. The ADS8508 and ADS8509 also provide anoutput synchronization pulse for ease of use with standard DSP processors. An innovative designallows operation from a singe 5V supply, while keeping power dissipation below 100mW.R1INR2INR3INCAPREFADS85099.8kΩ4.9kΩ2.5kΩ10kΩSuccessive Approximation Register and Control LogicBuffer4kΩR/C CS PWRDCDACInternal+2.5V RefComparatorSerialDataOutADS850x functional block diagram.*ADS8513 expected release date 3Q 07, ADS8506 expected release date 4Q 07.ClockEXT/INTBUSYSYNCDATACLKDATA16-Bit, 4MSPS, Fully Differential Input, microPower ADC with Parallel InterfaceADS8422Get samples, datasheets, evaluation modules and app reports at: www.ti.com/ADS8422Key Features• Fully differential input with pseudo-bipolarinput range: –4V to +4V• 16-bit NMC at 4MSPS• INL: 1LSB (typ)• SNR: –92dB• THD: –102dB 9typ) at 100kHz input• Internal reference (4.096V) andreference buffer• Single-supply operation capability• Low power: 155mW at 4MHz (typ);flexible power-down schemeApplications• DWDM• Instrumentation• High-speed, high-resolution, zero latencydata acquisition systems• Transducer interface• Medical instruments• Spectrum analysis•ATETexas Instruments 3Q 2007The ADS8422 is a 16-bit, 4MSPS SAR ADC that includes a full 16-bit interface and an 8-bitoption where data is ready using two 8-bit read cycles if necessary. It has a fully differential,pseudo-bipolar input.+IN–INCOMMOUTREFINREFOUTADS84221/2ADS8422 functional block diagram.CDAC4.096-VInternal ReferenceSARComparatorClockOutputLatchesand 3-StateDriversConversionandControl LogicBYTE16-/18-BITPARALLEL DATAOUTPUT BUSPD2RESET/PD1CONVSTBUSYCSRDAmplifier and Data Converter Selection Guide
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6 Amplifiers➔Texas Instruments (T
Page 8 and 9: 8Amplifiers➔Precision Operational
Page 10 and 11: 10 Amplifiers➔Precision Operation
Page 12 and 13: 12➔AmplifiersPrecision Operationa
Page 14 and 15: 14AmplifiersPrecision Operational A
Page 16 and 17: 16Amplifiers➔High-Speed Amplifier
Page 18 and 19: 18➔AmplifiersHigh-Speed Amplifier
Page 20 and 21: 20 Amplifiers➔Video AmplifiersVid
Page 22 and 23: 22Amplifiers➔Video AmplifiersVide
Page 24 and 25: 24➔AmplifiersComparatorsLow-Power
Page 26 and 27: 26 Amplifiers➔Difference Amplifie
Page 28 and 29: 28 Amplifiers➔Analog Current Shun
Page 30 and 31: 30 Amplifiers➔Instrumentation Amp
Page 32 and 33: 32➔AmplifiersSingle-Supply Instru
Page 34 and 35: 34 Amplifiers➔Programmable Gain A
Page 36 and 37: 36➔AmplifiersVoltage-Controlled G
Page 38 and 39: 38➔AmplifiersAudio AmplifiersPure
Page 40 and 41: 40Amplifiers➔Audio Power Amplifie
Page 42 and 43: 42 Amplifiers➔Power Amplifiers an
Page 44 and 45: 44 Amplifiers➔Pulse Width Modulat
Page 46 and 47: 46➔AmplifiersSensor Conditioners
Page 48 and 49: 48 Amplifiers➔Integrating Amplifi
Page 50 and 51: 50 Amplifiers➔Amplifiers for Driv
Page 52 and 53: 52 ADCs by Architecture➔Delta-Sig
Page 54 and 55: 54➔ADCs by ArchitectureDelta-Sigm
Page 56 and 57: 56 ADCs by Architecture➔Wide Band
Page 60 and 61: 60ADCs by Architecture➔SAR ADCs18
Page 62 and 63: 62➔ADCs by ArchitectureSuccessive
Page 64 and 65: 64 ADCs by Architecture➔Pipeline
Page 66 and 67: 66➔ADCs by ArchitecturePipeline A
Page 68 and 69: 68➔ADCs by ArchitecturePipeline A
Page 70 and 71: 70➔DACs by ArchitectureHigh-Accur
Page 72 and 73: 72DACs by Architecture➔High-Accur
Page 74 and 75: 74DACs by Architecture➔High-Accur
Page 76 and 77: 76DACs by Architecture➔Current St
Page 78 and 79: 78➔Analog Monitoring and ControlA
Page 80 and 81: 80 Analog Monitoring and Control➔
Page 82 and 83: 82Voltage References➔ Voltage Ref
Page 84 and 85: 84➔Temperature SensorsTemperature
Page 86 and 87: 86Quick Reference Selection TableAD
Page 94 and 95: 94Quick Reference Selection TableDA
Page 96 and 97: 96Quick Reference Selection TableDA
Page 98 and 99: 98Quick Reference Audio Selection T
Page 100 and 101: 100Quick Reference Audio Selection
Page 102 and 103: 102➔Design and Evaluation ToolsFi
Page 104 and 105: 104➔Design and Evaluation ToolsSi
Page 106 and 107: 106➔Design and Evaluation ToolsEv
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108➔Design and Evaluation ToolsDa
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110➔Design and Evaluation ToolsDa
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112➔Design and Evaluation ToolsAm
Page 114 and 115:
114➔Design and Evaluation ToolsAp
Page 116 and 117:
116Device Index➔DevicePageDAC7643
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118Device Index➔DevicePageTLV2544
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Texas Instruments Incorporated14950
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Amplifier and Data Converter Selection Guide (Rev. B

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