Amplifier and Data Converter Selection Guide (Rev. B

64 ADCs by Architecture➔Pipeline ADCsAnalog-to-digital converters featuring samplingrates of 10s of MSPS are likely based on thepipeline architecture. The pipelined ADCconsists of N cascaded stages. The concurrentoperation of all pipeline stages makes thisarchitecture suitable for achieving very highconversion rates. The stages themselves areessentially identical, lined up in an assemblyline fashion and designed to convert only aportion of the analog sample. The digitaloutput of each stage is combined to producethe parallel data output bits. A new digitizedsample becomes available with every clockcycle. The internal combination process itselfrequires a digital delay, which is commonlyreferred to as the pipeline delay, or datalatency. For most applications this is not alimitation since the delay, expressed innumber of clock cycles, is a constant and canbe accounted for.One of the key architectural features ofpipeline ADCs that allows high dynamicperformances at high signal frequencies isthe differential signal input. The differentialinput configuration results in the optimumdynamic range since it leads to smaller signalamplitude and a reduction in even-orderharmonics. Almost all high-speed pipelineADCs use a single-supply voltage, rangingfrom +5V down to +1.8V. Therefore, mostrequire the analog input to operate with acommon-mode voltage, which typically is atthe mid-supply level. This common-mode orinput bias requirement comes into considerationwhen defining the input interfacecircuitry that will drive the ADC. Switchedcapacitor inputs should also be considered.Technical InformationPipeline ADCs also employ the basicidea of moving charge samples, whichrepresent the input voltage level at theparticular sample incident, from one stage tothe next. The differential pipeline structure ishighly repetitive where each of the pipelinestages consists of a sample-and-hold (S/H),a low-resolution ADC and DAC, and a summingcircuit that includes aninterstage amplifier to provide gain.The analog signal is sampled with the firstS/H circuit, which may also facilitate a singleendedto differential conversion. This S/H isone of the most critical blocks as it typicallysets the performance limits of the converter.As the captured sample passes through thepipeline, the conversion is iterated by thestages that refine the conversion withincreasing resolution as they pass theremainder signal from stage to stage. Eachstage performs an analog-to-digital conversion,and a back-conversion to analog. Thedifference between the D/A output and theheld input is the residue that is amplifiedand sent to the next stage where thisprocess is repeated.In order to properly design the interface circuitto the pipeline ADC, its switched-capacitorinput structure needs to be considered. Theinput impedance of the pipeline converterrepresents a capacitive load to the drivingsource. Furthermore, it is dynamic since it isa function of the sampling rate (1/f s ). Theinternal switches generate small transientcurrent pulses that may affect the settlingbehavior of the source. To reduce the effectsof this switched-capacitor, input seriesresistors and a shunt capacitor are typicallyrecommended. This will also ensurestability and fast settling of the drivingamplifier.Sample/HoldADCINPUTC sN OUTPUT BITSPER STAGEDACV1 +Stage 1 Stage 2LatchGain = 2AmplifiedAnalogResidueN EFFECTIVE BITS OUT+To select an appropriate interface circuitconfiguration, it is important to determinewhether the application is time domain innature (e.g. CCD-based imaging system) or afrequency domain application (e.g. communicationsystem). Time domain applicationsusually have an input frequency bandwidththat includes DC. Frequency domain applications,on the other hand, are typically accoupled.The key converter specificationshere are SFDR, SNR, aperture jitter andanalog input bandwidth; the last twospecifications particularly apply toundersampling applications. The optimuminterface configuration will depend onwhether the application calls for widedynamic range (SFDR), or low noise (SNR),or both.Critical to the performance of high-speedADCs is the clock signal, since a variety ofinternal timing signals are derived from thisclock. Pipeline ADCs may use both the risingand falling clock edge to trigger internalfunctions. For example, sampling occurs onthe rising edge prompting this edge to havevery low jitter. Clock jitter leads to aperturejitter, which can be the ultimate limitation inachieving good SNR performance. Particularlyin undersampling applications, specialconsideration should be given to clock jitter.V0ANALOG PIPELINE+ ++LatchPipeline ADCs consist of consecutive stages, each containinga S/H, a low-resolution ADC and DAC, and a summing circuitthat includes an interstage amplifier to provide gain.Stage NDIGITAL OUTPUTWORDAmplifier and Data Converter Selection Guide Texas Instruments 3Q 2007