Amplifier and Data Converter Selection Guide (Rev. B

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64 ADCs by Architecture➔Pipeline ADCsAnalog-to-digital converters featuring samplingrates of 10s of MSPS are likely based on thepipeline architecture. The pipelined ADCconsists of N cascaded stages. The concurrentoperation of all pipeline stages makes thisarchitecture suitable for achieving very highconversion rates. The stages themselves areessentially identical, lined up in an assemblyline fashion and designed to convert only aportion of the analog sample. The digitaloutput of each stage is combined to producethe parallel data output bits. A new digitizedsample becomes available with every clockcycle. The internal combination process itselfrequires a digital delay, which is commonlyreferred to as the pipeline delay, or datalatency. For most applications this is not alimitation since the delay, expressed innumber of clock cycles, is a constant and canbe accounted for.One of the key architectural features ofpipeline ADCs that allows high dynamicperformances at high signal frequencies isthe differential signal input. The differentialinput configuration results in the optimumdynamic range since it leads to smaller signalamplitude and a reduction in even-orderharmonics. Almost all high-speed pipelineADCs use a single-supply voltage, rangingfrom +5V down to +1.8V. Therefore, mostrequire the analog input to operate with acommon-mode voltage, which typically is atthe mid-supply level. This common-mode orinput bias requirement comes into considerationwhen defining the input interfacecircuitry that will drive the ADC. Switchedcapacitor inputs should also be considered.Technical InformationPipeline ADCs also employ the basicidea of moving charge samples, whichrepresent the input voltage level at theparticular sample incident, from one stage tothe next. The differential pipeline structure ishighly repetitive where each of the pipelinestages consists of a sample-and-hold (S/H),a low-resolution ADC and DAC, and a summingcircuit that includes aninterstage amplifier to provide gain.The analog signal is sampled with the firstS/H circuit, which may also facilitate a singleendedto differential conversion. This S/H isone of the most critical blocks as it typicallysets the performance limits of the converter.As the captured sample passes through thepipeline, the conversion is iterated by thestages that refine the conversion withincreasing resolution as they pass theremainder signal from stage to stage. Eachstage performs an analog-to-digital conversion,and a back-conversion to analog. Thedifference between the D/A output and theheld input is the residue that is amplifiedand sent to the next stage where thisprocess is repeated.In order to properly design the interface circuitto the pipeline ADC, its switched-capacitorinput structure needs to be considered. Theinput impedance of the pipeline converterrepresents a capacitive load to the drivingsource. Furthermore, it is dynamic since it isa function of the sampling rate (1/f s ). Theinternal switches generate small transientcurrent pulses that may affect the settlingbehavior of the source. To reduce the effectsof this switched-capacitor, input seriesresistors and a shunt capacitor are typicallyrecommended. This will also ensurestability and fast settling of the drivingamplifier.Sample/HoldADCINPUTC sN OUTPUT BITSPER STAGEDACV1 +Stage 1 Stage 2LatchGain = 2AmplifiedAnalogResidueN EFFECTIVE BITS OUT+To select an appropriate interface circuitconfiguration, it is important to determinewhether the application is time domain innature (e.g. CCD-based imaging system) or afrequency domain application (e.g. communicationsystem). Time domain applicationsusually have an input frequency bandwidththat includes DC. Frequency domain applications,on the other hand, are typically accoupled.The key converter specificationshere are SFDR, SNR, aperture jitter andanalog input bandwidth; the last twospecifications particularly apply toundersampling applications. The optimuminterface configuration will depend onwhether the application calls for widedynamic range (SFDR), or low noise (SNR),or both.Critical to the performance of high-speedADCs is the clock signal, since a variety ofinternal timing signals are derived from thisclock. Pipeline ADCs may use both the risingand falling clock edge to trigger internalfunctions. For example, sampling occurs onthe rising edge prompting this edge to havevery low jitter. Clock jitter leads to aperturejitter, which can be the ultimate limitation inachieving good SNR performance. Particularlyin undersampling applications, specialconsideration should be given to clock jitter.V0ANALOG PIPELINE+ ++LatchPipeline ADCs consist of consecutive stages, each containinga S/H, a low-resolution ADC and DAC, and a summing circuitthat includes an interstage amplifier to provide gain.Stage NDIGITAL OUTPUTWORDAmplifier and Data Converter Selection Guide Texas Instruments 3Q 2007
ADCs by ArchitecturePipeline ADCs65➔12-Bit, 125MSPS, Quad Channel ADC with Serial LVDS InterfaceADS6425Get datasheets at: www.ti.com/ADS6425Key Features• 12-bit resolution at 125MSPS• Resolution: 12-bit• Total power: 1.65W• SNR: 70.3dBFS at F IN = 50MHz• SFDR: 83dBc at F IN = 50MHz, 0dB gain,3.5dB coarse gain and up to 6dBprogrammable fine gain for SFDR/SNRtrade-off• Serialized LVDS outputs withprogrammable internal termination option• No external decoupling required for references• Analog and digital supply: 3.3V• Packaging: QFN-64Applications• Base station IF receivers• Diversity receivers• Medical imaging• Test equipmentThe ADS6425 is a high-performance, 12-bit, 125MSPS quad-channel ADC with serial LVDS dataoutputs to reduce the number of interface lines to allow for higher system integration density. Itincludes a 3.5dB coarse gain option that can be used to improve SFDR performance with littledegradation in SNR. Fine gain options exist up to 6dB with programmable 1dB steps. The LVDSoutput buffers have features such as programmable LVDS currents, current doubling modes andinternal termination options. These can be used to widen eye-openings and improve signalintegrity, easing capture by the receiver.ADS6425 functionalblock diagram.CLKPCLKMINA_PINA_MIND_PIND_MVCM≈AVDDAGNDADS6425SHASHAReference12-BitADC12-BitADCREFPREFMCAPPLLParallelInterfaceLVDDLGNDDigitalEncoder andSerializerDigitalEncoder andSerializerBIT ClockFRAME ClockSerialInterface≈DCLKPDCLKMFCLKPFCLKMDA0_PDA0_MDA1_PDA1_MDD0_PDD0_MDD1_PDD1_M14-Bit, 80MSPS/105MSPS ADCsADS5424, ADS5423, ADS5433PDNCFG1CFG2CFG3CFG4SENSDATASCLKRESETGet datsheets and app reports at: www.ti.com/sc/device/PARTnumber (Replace PARTnumber with ADS5424, ADS5423 or ADS5433)Key Features• Resolution: 14-bit• Sample rate: 80/105MSPS• High SNR: 74.4dBc at30MHz IF (ADS5433)• High SFDR: 96.5dBc at30MHz IF (ADS5433)• Differential input range: 2.2Vpp• Supply operation: 5V• 3.3V CMOS-compatible outputs• Total power dissipation: 1.85W• 2s complement output format• On-chip input analog buffer, track andhold, and reference circuit• Pin compatible to AD6644/45• Industrial temperature range:–40°C to +85°C• Packaging: 52-lead HTQFP with exposedheatsinkApplications• Single and multichannel digital receivers• Base station infrastructure• Instrumentation• Video and imagingTexas Instruments 3Q 2007The ADS5433 is a new member of the high-performance wideband, bipolaranalog-to-digital converter family which includes the ADS5423 (14-bit, 80MSPS) andADS5424 (14-bit, 105MSPS). The ADS5433 is a 14-bit, 80 MSPS ADC optimized for highSFDR performance up to 100MHz input frequency; offering users up to 11dB better SFDRperformance when compared to 14-bit and 16-bit ADCs with similar sample rates. Thisincreased SFDR performance allows for increased receiver sensitivity and betteradjacent channel rejection in wireless receiver designs.AINAINVREFC1C2CLK+CLK–A1ReferenceTH1TimingADC1TH2ADS542x family functional block diagram.+DAC1Σ–A2ADC25 5Digital Error CorrectionDAC2+Σ–AVDDDMID OVR DRY D[13:0] GNDTH3A3DRVDDADC3ADS5424Amplifier and Data Converter Selection Guide6
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6 Amplifiers➔Texas Instruments (T
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8Amplifiers➔Precision Operational
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10 Amplifiers➔Precision Operation
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12➔AmplifiersPrecision Operationa
Page 14 and 15: 14AmplifiersPrecision Operational A
Page 16 and 17: 16Amplifiers➔High-Speed Amplifier
Page 18 and 19: 18➔AmplifiersHigh-Speed Amplifier
Page 20 and 21: 20 Amplifiers➔Video AmplifiersVid
Page 22 and 23: 22Amplifiers➔Video AmplifiersVide
Page 24 and 25: 24➔AmplifiersComparatorsLow-Power
Page 26 and 27: 26 Amplifiers➔Difference Amplifie
Page 28 and 29: 28 Amplifiers➔Analog Current Shun
Page 30 and 31: 30 Amplifiers➔Instrumentation Amp
Page 32 and 33: 32➔AmplifiersSingle-Supply Instru
Page 34 and 35: 34 Amplifiers➔Programmable Gain A
Page 36 and 37: 36➔AmplifiersVoltage-Controlled G
Page 38 and 39: 38➔AmplifiersAudio AmplifiersPure
Page 40 and 41: 40Amplifiers➔Audio Power Amplifie
Page 42 and 43: 42 Amplifiers➔Power Amplifiers an
Page 44 and 45: 44 Amplifiers➔Pulse Width Modulat
Page 46 and 47: 46➔AmplifiersSensor Conditioners
Page 48 and 49: 48 Amplifiers➔Integrating Amplifi
Page 50 and 51: 50 Amplifiers➔Amplifiers for Driv
Page 52 and 53: 52 ADCs by Architecture➔Delta-Sig
Page 54 and 55: 54➔ADCs by ArchitectureDelta-Sigm
Page 56 and 57: 56 ADCs by Architecture➔Wide Band
Page 58 and 59: 58 ADCs by Architecture➔SAR ADCsS
Page 60 and 61: 60ADCs by Architecture➔SAR ADCs18
Page 62 and 63: 62➔ADCs by ArchitectureSuccessive
Page 66 and 67: 66➔ADCs by ArchitecturePipeline A
Page 68 and 69: 68➔ADCs by ArchitecturePipeline A
Page 70 and 71: 70➔DACs by ArchitectureHigh-Accur
Page 72 and 73: 72DACs by Architecture➔High-Accur
Page 74 and 75: 74DACs by Architecture➔High-Accur
Page 76 and 77: 76DACs by Architecture➔Current St
Page 78 and 79: 78➔Analog Monitoring and ControlA
Page 80 and 81: 80 Analog Monitoring and Control➔
Page 82 and 83: 82Voltage References➔ Voltage Ref
Page 84 and 85: 84➔Temperature SensorsTemperature
Page 86 and 87: 86Quick Reference Selection TableAD
Page 94 and 95: 94Quick Reference Selection TableDA
Page 96 and 97: 96Quick Reference Selection TableDA
Page 98 and 99: 98Quick Reference Audio Selection T
Page 100 and 101: 100Quick Reference Audio Selection
Page 102 and 103: 102➔Design and Evaluation ToolsFi
Page 104 and 105: 104➔Design and Evaluation ToolsSi
Page 106 and 107: 106➔Design and Evaluation ToolsEv
Page 108 and 109: 108➔Design and Evaluation ToolsDa
Page 110 and 111: 110➔Design and Evaluation ToolsDa
Page 112 and 113: 112➔Design and Evaluation ToolsAm
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114➔Design and Evaluation ToolsAp
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116Device Index➔DevicePageDAC7643
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118Device Index➔DevicePageTLV2544
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Texas Instruments Incorporated14950
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Amplifier and Data Converter Selection Guide (Rev. B

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