Intel 631xESB/632xESB I/O Controller Hub - Viglen Download

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Revision HistoryDocumentNumberRevisionNumberDescriptionDate313082 -001 • Initial release of the document. May 2006§§36 Intel ® 631xESB/632xESB I/O Controller Hub Datasheet
Introduction1 Introduction1.1 About This DocumentThis specification is intended for Original Equipment Manufacturers designing andbuilding Intel ® 631xESB/632xESB I/O Controller Hub-based products. This manualassumes a working knowledge of the vocabulary and principles of PCI Express*, USB,IDE, AHCI, SATA, SMBus, PCI, PCI-X*, ACPI, ESI, JTAG, and LPC. Although somedetails of these features are described within this specification, refer to the individualindustry specifications listed in Table 1-1 for complete details.Table 1-1. Industry Specifications and Related Documents (Sheet 1 of 2)DocumentAdvanced Configuration and Power Interface, Version 2.0(ACPI)Locationhttp://www.acpi.info/spec.htmAES CBC-mode Cipher Algorithm, RFC 2451http://www.ietf.org/rfc/rfc2451.txt?number=2451Alert Standard Format Specification, Version 2.0http://www.dmtf.org/standards/standard_alert.phpAT Attachment - 6 with Packet Interface (ATA/ATAPI - 6) http://T13.org (T13 1410D)Audio Codec ‘97 Component Specification, Version 2.3(AC’97)Enhanced Host Controller Interface Specification forUniversal Serial Bus, Revision 1.0 (EHCI)HMAC Key-Hashing for Message Authentication, RFC 2104IA-PC HPET (High Precision Event Timers) Specification,Revision 0.98aIEEE 802.3 Fast EthernetIEEE Standard Test Access Port and Boundary ScanArchitecture 1149.1 SpecificationsIntel ® 631xESB/632xESB I/O Controller Hub EDSSpecification UpdateIPMI v1.5 SpecificationLow Pin Count Interface Specification, Revision 1.1 (LPC)MD5 Message Digest algorithm, RFC 1321PCI Express* Base Specification, Revision 1.0aPCI Local Bus Specification, Revision 2.3 (PCI)PCI Power Management Specification, Revision 1.1PCI Standard Hot-Plug Controller Specification Rev 1.0PCI-X Electrical and Mechanical Addendum to the PCI BaseSpecification, Revision 2.0aPCI-X Protocol Addendum to the PCI Base Specification,Revision 2.0aPCI-X Protocol Addendum to the PCI Local Bus SpecificationRevision 2.0http://www.intel.com/labs/media/audio/index.htmhttp://developer.intel.com/technology/usb/ehcispec.htmhttp://www.ietf.org/rfc/rfc2104.txt?number=2104http://www.intel.com/labs/platcomp/hpet/hpetspec.htmhttp://standards.ieee.orghttp://standards.ieee.org/reading/ieee/std_public/description/testtech/1149.1-1990_desc.htmlhttp://developer.intel.comhttp://www.intel.com/design/servers/ipmi/spec.htmhttp://developer.intel.com/design/chipsets/industry/lpc.htmhttp://www.ietf.org/rfc/rfc1321.txt?number=1321http://www.pcisig.com/specificationshttp://www.pcisig.com/specificationshttp://www.pcisig.com/specificationshttp://www.pcisig.com/specificationshttp://www.pcisig.com/specificationshttp://www.pcisig.com/specificationshttp://www.pcisig.com/specificationsIntel ® 631xESB/632xESB I/O Controller Hub Datasheet 37
Page 1: Intel ® 631xESB/632xESB I/OControl
Page 4 and 5: Intel ® 631xESB/632xESB I/O Contro
Page 8 and 9: 5.20.3 Data Encoding and Bit Stuffi
Page 10 and 11: 12.1.60 D30IP - Device 30 Interrupt
Page 12 and 13: 14.1.39 VC0CAP - VC0 Resource Capab
Page 14 and 15: 15.1.4 PCISTS - PCI Status Register
Page 17 and 18: 17.1.6 PI - Programming Interface R
Page 19 and 20: 19.1.19 PCID - Programmable Codec I
Page 21 and 22: 21.3.1 TCW - Timer Control Word Reg
Page 23 and 24: 22.1.27 ATS - APM Trapping Register
Page 25 and 26: 24.2.12 AUX_CTL - Auxiliary Control
Page 27 and 28: 25.3.1 DID - Device Identification
Page 29 and 30: 25.5.20 USB_RELNUM - USB Release Nu
Page 31 and 32: 5-22 USB Legacy Keyboard Flow Diagr
Page 33 and 34: 5-29 Address Shifting in 16-Bit I/O
Page 35: 16-3 Run/Stop, Debug Bit Interactio
Page 39 and 40: IntroductionChapter 9, “Mechanica
Page 41 and 42: Introduction• Dual Gigabit MAC wi
Page 43 and 44: IntroductionThe PCI-X interface on
Page 45 and 46: IntroductionAdvanced Programmable I
Page 47 and 48: IntroductionAC’97 2.3 ControllerT
Page 49 and 50: Signal Descriptions2 Signal Descrip
Page 51 and 52: Signal DescriptionsFigure 2-1.Intel
Page 53 and 54: Signal Descriptions2.1 Enterprise S
Page 55 and 56: Signal DescriptionsTable 2-5. PCI I
Page 57 and 58: Signal Descriptions2.4 PCI/PCI-X* B
Page 59 and 60: Signal Descriptions2.5 PCI/PCI-X* B
Page 61 and 62: Signal DescriptionsTable 2-10. PCI-
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Page 67 and 68: Signal Descriptions2.12 LPC Interfa
Page 69 and 70: Signal DescriptionsTable 2-19. Proc
Page 71 and 72: Signal DescriptionsTable 2-21. Powe
Page 73 and 74: Signal Descriptions2.21 RS-232 Inte
Page 75 and 76: Signal DescriptionsTable 2-29. Gene
Page 77 and 78: Signal DescriptionsTable 2-30. Misc
Page 79 and 80: Signal Descriptions2.28 Pin StrapsT
Page 81 and 82: Signal DescriptionsTable 2-32. Func
Page 83 and 84: Signal DescriptionsTable 2-33.Intel
Page 85 and 86: Intel ® 631xESB/632xESB I/O Contro
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Intel ® 631xESB/632xESB I/O Contro
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Functional Description5 Functional
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Functional Description5.1 PCI Expre
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Functional Description• On-die te
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Functional DescriptionTable 5-4.PCI
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Functional DescriptionA new registe
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Functional DescriptionTable 5-7. St
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Functional DescriptionIntel ® 631x
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Functional DescriptionM66EN Pin Han
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Functional Description5.1.3.1.2 Ove
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Functional DescriptionFigure 5-5 is
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Functional Description5.1.3.1.7 PCI
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Functional DescriptionTable 5-12.PC
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Functional DescriptionIf RCTL.PIE i
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Functional Description5.2.4.4 SMI/S
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Functional Description5.3.2.8 Memor
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Functional Description5.4 Integrate
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Functional Description5.4.2 Packet
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Functional DescriptionTable 5-16.St
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Functional DescriptionTable 5-19. A
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Functional Description• Reception
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Functional DescriptionOffset# ofByt
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Functional Descriptionits link part
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Functional Description5.4.9.1 Flash
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Functional DescriptionFigure 5-9.Se
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Functional DescriptionIn any config
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Functional Description• External
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Functional DescriptionBIOS and EFI
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Functional Description5.5.5.1.5 PCI
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Functional DescriptionFigure 5-12.
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Functional DescriptionThe HOST inte
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Functional Description5.6.1.1 LPC C
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Functional Description5.6.1.6 SYNC
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Functional Descriptionany other pur
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Functional DescriptionThe address s
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Functional DescriptionThere may be
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Functional Descriptionarbitrate aft
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Functional DescriptionTable 5-30.Co
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Functional DescriptionTable 5-31. I
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Functional Description5.10.2.1 ICW1
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Functional Description5.10.4.5 Poll
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Functional DescriptionInternal sour
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Functional Description2. Internally
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Functional Description5.12 Serial I
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Functional DescriptionTable 5-38. D
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Functional Description5.14.1.1 A20M
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Functional Description5.14.2 Dual-P
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Functional DescriptionTable 5-43.Ge
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Functional DescriptionTable 5-46. C
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Functional Description5.15.5.1 Tran
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Functional DescriptionIt is importa
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Functional Descriptionprocessor is
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Functional Description5.15.8.2 RI#
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Functional Description3. BIOS conti
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Functional Description5.15.9.3 Read
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Functional Description• Signals w
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Functional Descriptiona. The SMLink
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Functional Description5.16.1.6 Dete
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Functional Description8. After step
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Functional DescriptionTable 5-57. H
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Functional DescriptionData prefetch
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Functional Description4. The Bus Ma
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Functional Descriptioninternal line
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Functional Description5.18.1.2 48-B
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Functional DescriptionWhen an opera
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Functional Description3. Set PxIE.P
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Functional Description3. Software s
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Functional Description5.20.3 Data E
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Functional Descriptionthe transfer
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Functional DescriptionTable 5-62.Bi
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Functional DescriptionTable 5-63.US
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Functional Description5.21.1.3 EHC
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Functional Descriptionaccesses main
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Functional DescriptionThe Port-Rout
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Functional Descriptionallows commun
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Functional Description— b. Resets
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Functional Description5.22 SMBusIf
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Functional DescriptionSend Byte / R
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Functional DescriptionTable 5-66.I
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Functional DescriptionThe 25 ms tim
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Functional DescriptionIf a Master l
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Functional DescriptionTable 5-73.Da
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Functional Description5.22.2 SMBus
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Functional Description12 bits of ad
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Functional Description.Table 5-78.F
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Functional Description5.23.2 AC-Lin
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Functional DescriptionSee your Plat
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Functional Descriptionengine moves
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Electrical Characteristics6 Electri
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Electrical CharacteristicsTable 6-4
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Electrical CharacteristicsFigure 6-
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Electrical Characteristics4. For co
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Component Ballout7 Component Ballou
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Component BalloutTable 7-2.Intel ®
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Signal Lists8 Signal Lists8.1 Intel
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Signal ListsIntel ® 631xESB/632xES
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Signal Lists8.2 Intel ® 631xESB/63
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Mechanical Specifications9 Mechanic
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Mechanical SpecificationsFigure 9-4
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Testability10 Testability10.1 JTAG
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Testability10.2.1 XOR Chain Testabi
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TestabilityTable 10-6. XOR Chain #3
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Testability2Table 10-8. XOR Chain #
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Register and Memory Mapping11 Regis
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Register and Memory MappingTable 11
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Register and Memory MappingTable 11
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Register and Memory MappingPCI cycl
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Chipset Configuration Registers12 C
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Chipset Configuration RegistersTabl
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Chipset Configuration RegistersBitD
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Chipset Configuration Registers12.1
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Chipset Configuration Registers00 =
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Chipset Configuration RegistersBits
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PCI Express* Bridge, Switch, and En
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Intel ® High Definition Audio Cont
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PCI Express* Configuration Register
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UHCI Controllers Registers16 UHCI C
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UHCI Controllers Registers16.1.4 PC
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UHCI Controllers RegistersBitDescri
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UHCI Controllers Registers16.1.17 U
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UHCI Controllers Registers16.2 USB
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UHCI Controllers RegistersTable 16-
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EHCI Controller Registers (D29:F7)1
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EHCI Controller Registers (D29:F7)B
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EHCI Controller Registers (D29:F7)T
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EHCI Controller Registers (D29:F7)T
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PCI-to-PCI Bridge Registers (D30:F0
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AC’97 Audio Controller Registers
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AC’97 Modem Controller Registers
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LPC Interface Bridge Registers (D31
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IDE Controller Registers (D31:F1)22
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IDE Controller Registers (D31:F1)Bi
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SATA Controller Registers (D31:F2)2
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SATA Controller Registers (D31:F2)B
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SATA Controller Registers (D31:F2)T
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SMBus Controller Registers (D31:F3)
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LAN Controller and BMC Registers (B
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High-Precision Event Timer Register
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