Intel 631xESB/632xESB I/O Controller Hub - Viglen Download

IntroductionTable 1-1. Industry Specifications and Related Documents (Sheet 2 of 2)DocumentPCI-X* Protocol Addendum to the PCI Local BusSpecification, Revision 2.0aSerial ATA Advanced Host Controller Interface (AHCI)Specification, Revision 1.0Serial ATA 1.0a SpecificationSerial ATA II: Extensions to Serial ATA 1.0, Revision 1.0SHA1 Secure Hash Algorithm RFC 3174System Management Bus Specification, Version 2.0 (SMBus)Universal Serial Bus Revision 2.0 Specification (USB)Universal Host Controller Interface, Revision 1.1 (UHCI)Wired for Management Baseline Version 2.0 (WfM)Locationhttp://www.pcisig.com/specificationshttp://www.serialata.orghttp://www.serialata.orghttp://www.serialata.orghttp://www.ietf.org/mail-archive/ietfannounce/Current/msg14881.htmlhttp://www.smbus.org/specs/http://www.usb.orghttp://developer.intel.com/design/USB/UHCI11D.htmhttp://www.intel.com/labs/manage/wfm/wfmspecs.htmThe following is a chapter-by-chapter description of the information in this document.Chapter 1, “Introduction”Introduces the Intel ® 631xESB/632xESB I/O Controller Hub, provides information onmanual organization, and gives a general overview of the component.Chapter 2, “Signal Descriptions”Provides a block diagram of the Intel ® 631xESB/632xESB I/O Controller Hub and adetailed description of each signal. Signals are arranged according to interface anddetails are provided as to the drive characteristics (Input/Output, Open Drain, and soon) of all signals.Chapter 3, “Intel ® 631xESB/632xESB I/O Controller Hub and System Clock Domains”Provides a list of each clock domain associated with the Intel ® 631xESB/632xESB I/OController Hub in an Intel ® 631xESB/632xESB I/O Controller Hub-based system.Chapter 4, “Intel ® 631xESB/632xESB I/O Controller Hub Pin States”Provides a complete list of signals, their associated power well, their logic level in eachsuspend state, and their logic level before and after reset.Chapter 5, “Functional Description”Provides a detailed description of the functions in the Intel ® 631xESB/632xESB I/OController Hub. All PCI buses, devices and functions in this manual are abbreviatedusing the following nomenclature; Bus:Device:Function. This manual abbreviates busesas B0 and B1, devices as D8, D27, D28, D29, D30 and D31 and functions as F0, F1, F2,F3, F4, F5, F6 and F7. For example Device 31 Function 0 is abbreviated as D31:F0, Busn Device 0Function 0 is abbreviated as Bn:D0:F0.Chapter 6, “Electrical Characteristics”Provides all AC and DC characteristics including detailed timing diagrams.Chapter 7, “Component Ballout”Provides tables with each signal and its ball assignment in the 641-mBGA package, aswell as diagrams of the ballout grid.Chapter 8, “Signal Lists”Provides drawings of the physical dimensions and characteristics of the 641-mBGApackage.38 Intel ® 631xESB/632xESB I/O Controller Hub Datasheet