Intel 631xESB/632xESB I/O Controller Hub - Viglen Download

IntroductionTable 1-2. PCI Devices and Functions (Sheet 2 of 2)Bus:Device:FunctionBus n:Device 0:Function 0Bus n:Device 0:Function 1Bus n:Device 0:Function 2Bus n:Device 0:Function 3Bus n:Device 0:Function 4Bus n:Device 0:Function 5Bus n:Device 0:Function 7Function DescriptionLAN 0/LAN 1 ControllerLAN 0/LAN 1 ControllerIDE Redirection ControllerSerial Port Redirection ControllerIPMI/KCS0UHCI Redirection ControllerBT ControllerNote:The PCI-to-LPC bridge contains registers that control LPC, Power Management, System Management,GPIO, Processor Interface, RTC, Interrupts, Timers, and DMA.The following sub-sections provide an overview of the Intel ® 631xESB/632xESB I/OController Hub’s capabilities.Enterprise South Bridge Interface (ESI)Enterprise South Bridge Interface (ESI) is the chip-to-chip connection between theMemory Controller Hub (MCH) and I/O Controller Hub functions of the Intel ® 631xESB/632xESB I/O Controller Hub. Maximum realized bandwidth on this interface is 1 GB/s ineach direction simultaneously, for an aggregate of 2 GB/s. Base functionality iscompletely software-transparent, permitting current and legacy software to operatenormally.PCI Express* InterfacesThe Intel ® 631xESB/632xESB I/O Controller Hub provides 4 PCI Express Root Portswhich are compliant to the PCI Express* Base Specification Revision 1.0a. The PCIExpress Root Ports can be statically configured as four x1 ports or ganged together toform one x4 port. Each Root Port supports 250 MB/s bandwidth in each direction (500MB/s concurrent).An additional PCI Express interface is provided for connection to the Memory ControllerHub (MCH). Maximum realized bandwidth on this interface is 2 GB/s in each directionsimultaneously, for an aggregate of 4 GB/s. This PCI Express interface is also compliantwith the PCI Express* Base Specification Revision 1.0a, and supports x4 and x8 widths.Intel ® 631xESB/632xESB I/O Controller Hub also implement two x4 PCI ExpressDownstream Ports, maximum realized bandwidth on this interface is 1 GB/s in eachdirection simultaneously, for an aggregate of 2 GB/s. These two ports can also beconfigured as one x8 PCI Express port. This PCI Express interface is also compliant withthe PCI Express* Base Specification Revision 1.0a.PCI-X* Bus InterfaceThe Intel ® 631xESB/632xESB I/O Controller Hub provides a PCI-X* Bus interfacewhich can be independently configured as either a PCI Bus or a PCI-X Bus. Thisinterface supports conventional PCI and PCI-X Mode 1. PCI Bus extensions are alsosupported; these include 64-bit addressing outbound with the capability to assert DAC,and full 64-bit addressing inbound. The inbound packet size is based on cache line sizeof the platform.42 Intel ® 631xESB/632xESB I/O Controller Hub Datasheet