Intel 631xESB/632xESB I/O Controller Hub - Viglen Download

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IntroductionI/OAT is a platform feature that provides TCP acceleration using chipset and LAN HWoffload features and optimized IA software to provide high-performance, low CPUutilization networking.JTAGThe Intel ® 631xESB/632xESB I/O Controller Hub has a JTAG (TAP) port compliant withthe IEEE Standard Test Access Port and Boundary Scan Architecture 1149.1Specifications. The TAP controller is accessed serially through five dedicated pins. Thiscan be used for test and debug purposes. System board interconnects can be DC testedusing the boundary scan logic in pads. See Chapter 10 for more on Intel ® 631xESB/632xESB I/O Controller Hub testability.1.3 Intel ® 631xESB/632xESB I/O Controller Hub SKUDefinitionTable 1-3.Note:Intel ® 631xESB/632xESB I/O Controller Hub SKUsIntel ® 631xESB/632xESB I/O Controller Hub can be upgraded to full IAMT solutionIntel ® 631xESB/632xESBI/O Controller Hub SKUsIntel ® 6321ESB I/OController Hub 1(Enterprise)Intel ® 6311ESBI/O ControllerHub 11st x4 PCI Express* YES YES2nd x4 PCI Express YES YES2 x1 PCI Express (1st pair) YES YES2 x1 PCI Express (2nd pair) YES YESPCI-X* YES YES6 SATA YES YESDual GbE YES NOIntel ® I/O AccelerationTechnologyYESNOSERDES YES NONotes:1. Contact your local Intel Field Sales Representative for currently available Intel ® 631xESB/632xESB I/OController Hub SKUs.2. “Intel ® I/O Acceleration Technology” replaces prior “Diamond Peak Technology” codename.3. Intel ® Active Server Manager includes the following features: IPMI2.0 compliance, Intel ® Active ClientManager, FW SDK, and SMWG based interface.§48 Intel ® 631xESB/632xESB I/O Controller Hub Datasheet
Signal Descriptions2 Signal DescriptionsThis chapter provides a detailed description of each signal. The signals are arranged infunctional groups according to their associated interface.The “#” symbol at the end of the signal name indicates that the active, or assertedstate occurs when the signal is at a low voltage level. When “#” is not present, thesignal is asserted when at the high voltage level.The following notations are used to describe the signal type:IOODI/OI/ODOCA-inA-outT/sInput PinOutput PinOpen Drain Output PinBi-directional Input/Output PinBi-directional, open drain input/output signal.Open Collector Output PinAnalog Input PinAnalog Output PinTri-State is a bi-directional, tri-state input/output pin.Intel ® 631xESB/632xESB I/O Controller Hub Datasheet 49
Page 1: Intel ® 631xESB/632xESB I/OControl
Page 4 and 5: Intel ® 631xESB/632xESB I/O Contro
Page 8 and 9: 5.20.3 Data Encoding and Bit Stuffi
Page 10 and 11: 12.1.60 D30IP - Device 30 Interrupt
Page 12 and 13: 14.1.39 VC0CAP - VC0 Resource Capab
Page 14 and 15: 15.1.4 PCISTS - PCI Status Register
Page 17 and 18: 17.1.6 PI - Programming Interface R
Page 19 and 20: 19.1.19 PCID - Programmable Codec I
Page 21 and 22: 21.3.1 TCW - Timer Control Word Reg
Page 23 and 24: 22.1.27 ATS - APM Trapping Register
Page 25 and 26: 24.2.12 AUX_CTL - Auxiliary Control
Page 27 and 28: 25.3.1 DID - Device Identification
Page 29 and 30: 25.5.20 USB_RELNUM - USB Release Nu
Page 31 and 32: 5-22 USB Legacy Keyboard Flow Diagr
Page 33 and 34: 5-29 Address Shifting in 16-Bit I/O
Page 35 and 36: 16-3 Run/Stop, Debug Bit Interactio
Page 37 and 38: Introduction1 Introduction1.1 About
Page 39 and 40: IntroductionChapter 9, “Mechanica
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Page 43 and 44: IntroductionThe PCI-X interface on
Page 45 and 46: IntroductionAdvanced Programmable I
Page 47: IntroductionAC’97 2.3 ControllerT
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Intel ® 631xESB/632xESB I/O Contro
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Functional Description5 Functional
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Functional Description5.1 PCI Expre
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Functional Description• On-die te
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Functional DescriptionTable 5-4.PCI
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Functional DescriptionA new registe
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Functional DescriptionTable 5-7. St
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Functional DescriptionIntel ® 631x
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Functional DescriptionM66EN Pin Han
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Functional Description5.1.3.1.2 Ove
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Functional DescriptionFigure 5-5 is
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Functional Description5.1.3.1.7 PCI
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Functional DescriptionTable 5-12.PC
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Functional DescriptionIf RCTL.PIE i
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Functional Description5.2.4.4 SMI/S
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Functional Description5.3.2.8 Memor
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Functional Description5.4 Integrate
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Functional Description5.4.2 Packet
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Functional DescriptionTable 5-16.St
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Functional DescriptionTable 5-19. A
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Functional Description• Reception
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Functional DescriptionOffset# ofByt
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Functional Descriptionits link part
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Functional Description5.4.9.1 Flash
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Functional DescriptionFigure 5-9.Se
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Functional DescriptionIn any config
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Functional Description• External
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Functional DescriptionBIOS and EFI
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Functional Description5.5.5.1.5 PCI
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Functional DescriptionFigure 5-12.
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Functional DescriptionThe HOST inte
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Functional Description5.6.1.1 LPC C
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Functional Description5.6.1.6 SYNC
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Functional Descriptionany other pur
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Functional DescriptionThe address s
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Functional DescriptionThere may be
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Functional Descriptionarbitrate aft
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Functional DescriptionTable 5-30.Co
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Functional DescriptionTable 5-31. I
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Functional Description5.10.2.1 ICW1
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Functional Description5.10.4.5 Poll
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Functional DescriptionInternal sour
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Functional Description2. Internally
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Functional Description5.12 Serial I
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Functional DescriptionTable 5-38. D
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Functional Description5.14.1.1 A20M
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Functional Description5.14.2 Dual-P
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Functional DescriptionTable 5-43.Ge
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Functional DescriptionTable 5-46. C
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Functional Description5.15.5.1 Tran
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Functional DescriptionIt is importa
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Functional Descriptionprocessor is
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Functional Description5.15.8.2 RI#
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Functional Description3. BIOS conti
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Functional Description5.15.9.3 Read
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Functional Description• Signals w
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Functional Descriptiona. The SMLink
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Functional Description5.16.1.6 Dete
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Functional Description8. After step
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Functional DescriptionTable 5-57. H
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Functional DescriptionData prefetch
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Functional Description4. The Bus Ma
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Functional Descriptioninternal line
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Functional Description5.18.1.2 48-B
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Functional DescriptionWhen an opera
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Functional Description3. Set PxIE.P
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Functional Description3. Software s
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Functional Description5.20.3 Data E
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Functional Descriptionthe transfer
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Functional DescriptionTable 5-62.Bi
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Functional DescriptionTable 5-63.US
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Functional Description5.21.1.3 EHC
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Functional Descriptionaccesses main
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Functional DescriptionThe Port-Rout
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Functional Descriptionallows commun
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Functional Description— b. Resets
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Functional Description5.22 SMBusIf
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Functional DescriptionSend Byte / R
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Functional DescriptionTable 5-66.I
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Functional DescriptionThe 25 ms tim
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Functional DescriptionIf a Master l
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Functional DescriptionTable 5-73.Da
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Functional Description5.22.2 SMBus
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Functional Description12 bits of ad
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Functional Description.Table 5-78.F
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Functional Description5.23.2 AC-Lin
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Functional DescriptionSee your Plat
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Functional Descriptionengine moves
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Electrical Characteristics6 Electri
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Electrical CharacteristicsTable 6-4
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Electrical CharacteristicsFigure 6-
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Electrical Characteristics4. For co
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Component Ballout7 Component Ballou
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Component BalloutTable 7-2.Intel ®
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Signal Lists8 Signal Lists8.1 Intel
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Signal ListsIntel ® 631xESB/632xES
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Signal Lists8.2 Intel ® 631xESB/63
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Mechanical Specifications9 Mechanic
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Mechanical SpecificationsFigure 9-4
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Testability10 Testability10.1 JTAG
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Testability10.2.1 XOR Chain Testabi
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TestabilityTable 10-6. XOR Chain #3
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Testability2Table 10-8. XOR Chain #
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Register and Memory Mapping11 Regis
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Register and Memory MappingTable 11
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Register and Memory MappingTable 11
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Register and Memory MappingPCI cycl
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Chipset Configuration Registers12 C
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Chipset Configuration RegistersTabl
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Chipset Configuration RegistersBitD
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Chipset Configuration Registers12.1
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Chipset Configuration Registers00 =
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Chipset Configuration RegistersBits
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PCI Express* Bridge, Switch, and En
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PCI Express* Configuration Register
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UHCI Controllers Registers16 UHCI C
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UHCI Controllers Registers16.1.4 PC
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UHCI Controllers RegistersBitDescri
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UHCI Controllers Registers16.1.17 U
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UHCI Controllers Registers16.2 USB
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UHCI Controllers RegistersTable 16-
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EHCI Controller Registers (D29:F7)1
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EHCI Controller Registers (D29:F7)B
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EHCI Controller Registers (D29:F7)T
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EHCI Controller Registers (D29:F7)T
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PCI-to-PCI Bridge Registers (D30:F0
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AC’97 Audio Controller Registers
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AC’97 Modem Controller Registers
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LPC Interface Bridge Registers (D31
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IDE Controller Registers (D31:F1)22
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IDE Controller Registers (D31:F1)Bi
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SATA Controller Registers (D31:F2)2
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SATA Controller Registers (D31:F2)B
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SATA Controller Registers (D31:F2)T
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SMBus Controller Registers (D31:F3)
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