Intel 631xESB/632xESB I/O Controller Hub - Viglen Download

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Signal DescriptionsFigure 2-1.Intel ® 631xESB/632xESB I/O Controller Hub Interface Signals Block Diagram(Sheet 1 of 3)ESITXP[3:0],ESITXN[3:0]ESIRXP[3:0],ESIRXN[3:0]ESICLK100P,ESICLK100NESIICOMPIESIDCACESIRCOMPOAD[31:0]CBE[3:0]#DEVSEL#FRAME#GNT[3:0]#GNT[4]# / GPIO[48]GNT[5]# / GPO[17]GNT[6]# / GPO[16]IRDY#PARPCICLKPCIRST#PERR#PLOCK#PLTRST#PME#REQ[3:0]#REQ[4]# / GPI[40]REQ[5]# / GPI[1]REQ[6]# / GPI[0]SERR#STOP#TRDY#A20M#CPUSLP#FERR#IGNNE#INIT#INIT3_3V#INTRNMISMI#STPCLK#RCIN#A20GATECPUPWRGD / GPO [49]ESIPCIInterfaceProcessorInterfacePCIExpress*InterfacePCI/PCI-XBusInterfacePCI/PCI-XBusInterface64-bitExtensionPE0TP[3:0], PE0TN[3:0]PE0RP[3:0], PE0RN[3:0]PE1TP[3:0], PE1TN[3:0]PE1RP[3:0], PE1RN[3:0]PE2TP[3:0], PE2TN[3:0]PE2RP[3:0], PE2RN[3:0]PE4TP[7:0], PE4TN[7:0]PE4RP[3:0], PE4RN[3:0]PECLKP,PECLKNPEICOMPIPERCOMPOEXTINTR#HPCLKHPDTAPX133ENPXAD[31:0]PXCBE[3:0]#PXDEVSEL #PXFRAME#PXGNT[5:0]#PXIRDY#PXM66ENPXPARPXPCIRST#PXPCIXCAPPXPCLKIPXPCLKO[6:0]PXPERR#PXPLOCK#PXPME#PXPWROKPXREQ[5:0]#PXSERR#PXSTOP#PASTRAP 0PXTRDY#RSTIN#PXACK64#PXAD[63:32]PXCBE[7:4]#PXPAR64PXREQ64#Intel® 631xESB / 632xESBI/O Controller Hub50 Intel ® 631xESB/632xESB I/O Controller Hub Datasheet
Signal DescriptionsFigure 2-1.Intel ® 631xESB/632xESB I/O Controller Hub Interface Signals Block Diagram(Sheet 2 of 3)RCOMPHPX_SICHPX_SIDHPX_SIL#HPX_SLOT[3:0]HPX_SOCHPX_SODHPX_SOLHPX_SOLRHPX_PRST#/HPX_RST1#HPX_RST2#KumeranandSERDESInterfaceLINK_[1:0]SEICOMPISER_CLK_INSERCOMPOSERP0, SERN0SETP0, SETN0SERP1, SERN1SETP1, SETN1HPX_SIC/ HXPWRLED2#HPX_SID/ HXPCIXCAP1_2HPX_SIL#/HXCLKEN_1#HPX_SLOT[0]/HXMRL_2#HPX_SLOT[1]/ HXPRSNT1_1#HPX_SLOT[3:0]HPX_SLOT[3]/ HXPWRLED1#HPX_SOC/ HXPCIXCAP2_2HPX_SOD/HXCLKEN_2HPX_SOL/ HXBUTTON2#HPX_SOLR/ HXATNLED2#HXATNLED_1#HXPWREN_1PXGNT[3]#/HXPWREN_2PXGNT[4]#/HXBUSEN_2#PXGNT[5]#/HXBUSEN_1#PXIRQ[10]#/ HXPCIXCAP1_1PXIRQ[11]#/HXM66EN_1PXIRQ[12]#/HXM66EN_2PXIRQ[13]#/HXPWRFLT_2#PXIRQ[14]#/HXPWRFLT_1#PXIRQ[15]#/HXMRL1#PXIRQ[8]#/HXBUTTON_1#PXIRQ[9]#/HXPCIXCAP2_1PXREQ[3]#/HXPRSNT2_1#PXREQ[4]#/HXPRSNT2_2#PXREQ[5]#/HXPRSNT1_2#SERIRQPIRQ[D:A]#PIRQ[H:E]# / GPIO[5:2]IDEIRQPXIRQ[15:0]#PCI/PCI-XHot PlugInterfaceInterruptInterfaceIDEInterfaceSerial ATAInterfacePowerMgnt.DCS1#DCS3#DA[2:0]DD[15:0]DDREQDDACK#DIOR# DWSTB / RDMARDY#DIOW#/ DSTOPIORDY (DRSTB / WDMARDY#)SATA[0]GP / GPI [26]SATA[3:1]GP / GPI [31:29]SATA[5:4]GP /GPIO[13:12]SATA[5:0]RXP,SATA[5:0]RXNSATA[5:0]TXP,SATA[5:0]TXNSATA_CLKP,SATA_CLKNSATALED#SATARBIAS,SATARBIAS#SDATAOUT0/ GPO[23],SDATAOUT1/ GPIO[32]SLOAD/ GPO[21]SCLK/GPO[20]THRM#THRMTRIP#SYS_RESET#RSMRST#SLP_S3#SLP_S4#SLP_S5#PWROKPWRBTN#RI#WAKE#SUS_STAT# / LPCPD#SUSCLKVRMPWRGDIntel® 631xESB / 632xESBI/O Controller HubIntel ® 631xESB/632xESB I/O Controller Hub Datasheet 51
Page 1: Intel ® 631xESB/632xESB I/OControl
Page 4 and 5: Intel ® 631xESB/632xESB I/O Contro
Page 8 and 9: 5.20.3 Data Encoding and Bit Stuffi
Page 10 and 11: 12.1.60 D30IP - Device 30 Interrupt
Page 12 and 13: 14.1.39 VC0CAP - VC0 Resource Capab
Page 14 and 15: 15.1.4 PCISTS - PCI Status Register
Page 17 and 18: 17.1.6 PI - Programming Interface R
Page 19 and 20: 19.1.19 PCID - Programmable Codec I
Page 21 and 22: 21.3.1 TCW - Timer Control Word Reg
Page 23 and 24: 22.1.27 ATS - APM Trapping Register
Page 25 and 26: 24.2.12 AUX_CTL - Auxiliary Control
Page 27 and 28: 25.3.1 DID - Device Identification
Page 29 and 30: 25.5.20 USB_RELNUM - USB Release Nu
Page 31 and 32: 5-22 USB Legacy Keyboard Flow Diagr
Page 33 and 34: 5-29 Address Shifting in 16-Bit I/O
Page 35 and 36: 16-3 Run/Stop, Debug Bit Interactio
Page 37 and 38: Introduction1 Introduction1.1 About
Page 39 and 40: IntroductionChapter 9, “Mechanica
Page 41 and 42: Introduction• Dual Gigabit MAC wi
Page 43 and 44: IntroductionThe PCI-X interface on
Page 45 and 46: IntroductionAdvanced Programmable I
Page 47 and 48: IntroductionAC’97 2.3 ControllerT
Page 49: Signal Descriptions2 Signal Descrip
Page 53 and 54: Signal Descriptions2.1 Enterprise S
Page 55 and 56: Signal DescriptionsTable 2-5. PCI I
Page 57 and 58: Signal Descriptions2.4 PCI/PCI-X* B
Page 59 and 60: Signal Descriptions2.5 PCI/PCI-X* B
Page 61 and 62: Signal DescriptionsTable 2-10. PCI-
Page 63 and 64: Signal DescriptionsTable 2-10. PCI-
Page 65 and 66: Signal DescriptionsTable 2-13. Seri
Page 67 and 68: Signal Descriptions2.12 LPC Interfa
Page 69 and 70: Signal DescriptionsTable 2-19. Proc
Page 71 and 72: Signal DescriptionsTable 2-21. Powe
Page 73 and 74: Signal Descriptions2.21 RS-232 Inte
Page 75 and 76: Signal DescriptionsTable 2-29. Gene
Page 77 and 78: Signal DescriptionsTable 2-30. Misc
Page 79 and 80: Signal Descriptions2.28 Pin StrapsT
Page 81 and 82: Signal DescriptionsTable 2-32. Func
Page 83 and 84: Signal DescriptionsTable 2-33.Intel
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Functional Description5 Functional
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Functional Description5.1 PCI Expre
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Functional Description• On-die te
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Functional DescriptionTable 5-4.PCI
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Functional DescriptionA new registe
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Functional DescriptionTable 5-7. St
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Functional DescriptionIntel ® 631x
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Functional DescriptionM66EN Pin Han
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Functional Description5.1.3.1.2 Ove
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Functional DescriptionFigure 5-5 is
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Functional Description5.1.3.1.7 PCI
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Functional DescriptionTable 5-12.PC
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Functional DescriptionIf RCTL.PIE i
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Functional Description5.2.4.4 SMI/S
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Functional Description5.3.2.8 Memor
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Functional Description5.4 Integrate
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Functional Description5.4.2 Packet
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Functional DescriptionTable 5-16.St
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Functional DescriptionTable 5-19. A
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Functional Description• Reception
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Functional DescriptionOffset# ofByt
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Functional Descriptionits link part
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Functional Description5.4.9.1 Flash
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Functional DescriptionFigure 5-9.Se
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Functional DescriptionIn any config
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Functional Description• External
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Functional DescriptionBIOS and EFI
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Functional Description5.5.5.1.5 PCI
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Functional DescriptionFigure 5-12.
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Functional DescriptionThe HOST inte
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Functional Description5.6.1.1 LPC C
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Functional Description5.6.1.6 SYNC
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Functional Descriptionany other pur
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Functional DescriptionThe address s
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Functional DescriptionThere may be
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Functional Descriptionarbitrate aft
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Functional DescriptionTable 5-30.Co
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Functional DescriptionTable 5-31. I
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Functional Description5.10.2.1 ICW1
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Functional Description5.10.4.5 Poll
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Functional DescriptionInternal sour
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Functional Description2. Internally
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Functional Description5.12 Serial I
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Functional DescriptionTable 5-38. D
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Functional Description5.14.1.1 A20M
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Functional Description5.14.2 Dual-P
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Functional DescriptionTable 5-43.Ge
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Functional DescriptionTable 5-46. C
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Functional Description5.15.5.1 Tran
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Functional DescriptionIt is importa
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Functional Descriptionprocessor is
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Functional Description5.15.8.2 RI#
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Functional Description3. BIOS conti
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Functional Description5.15.9.3 Read
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Functional Description• Signals w
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Functional Descriptiona. The SMLink
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Functional Description5.16.1.6 Dete
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Functional Description8. After step
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Functional DescriptionTable 5-57. H
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Functional DescriptionData prefetch
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Functional Description4. The Bus Ma
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Functional Descriptioninternal line
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Functional Description5.18.1.2 48-B
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Functional DescriptionWhen an opera
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Functional Description3. Set PxIE.P
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Functional Description3. Software s
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Functional Description5.20.3 Data E
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Functional Descriptionthe transfer
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Functional DescriptionTable 5-62.Bi
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Functional DescriptionTable 5-63.US
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Functional Description5.21.1.3 EHC
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Functional Descriptionaccesses main
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Functional DescriptionThe Port-Rout
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Functional Descriptionallows commun
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Functional Description— b. Resets
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Functional Description5.22 SMBusIf
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Functional DescriptionSend Byte / R
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Functional DescriptionTable 5-66.I
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Functional DescriptionThe 25 ms tim
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Functional DescriptionIf a Master l
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Functional DescriptionTable 5-73.Da
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Functional Description5.22.2 SMBus
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Functional Description12 bits of ad
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Functional Description.Table 5-78.F
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Functional Description5.23.2 AC-Lin
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Functional DescriptionSee your Plat
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Functional Descriptionengine moves
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Electrical Characteristics6 Electri
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Electrical CharacteristicsTable 6-4
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Electrical CharacteristicsFigure 6-
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Electrical Characteristics4. For co
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Component Ballout7 Component Ballou
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Component BalloutTable 7-2.Intel ®
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Signal Lists8 Signal Lists8.1 Intel
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Signal ListsIntel ® 631xESB/632xES
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Page 317 and 318:
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Signal Lists8.2 Intel ® 631xESB/63
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Page 335 and 336:
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Mechanical Specifications9 Mechanic
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Mechanical SpecificationsFigure 9-4
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Testability10 Testability10.1 JTAG
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Testability10.2.1 XOR Chain Testabi
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TestabilityTable 10-6. XOR Chain #3
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Testability2Table 10-8. XOR Chain #
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Register and Memory Mapping11 Regis
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Register and Memory MappingTable 11
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Register and Memory MappingTable 11
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Register and Memory MappingPCI cycl
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Chipset Configuration Registers12 C
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Chipset Configuration RegistersTabl
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Chipset Configuration RegistersBitD
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Chipset Configuration Registers12.1
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Page 377 and 378:
Page 379 and 380:
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Chipset Configuration Registers00 =
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Chipset Configuration RegistersBits
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Page 391 and 392:
Page 393 and 394:
Page 395 and 396:
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PCI Express* Bridge, Switch, and En
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Intel ® High Definition Audio Cont
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Page 531 and 532:
Page 533 and 534:
Page 535 and 536:
PCI Express* Configuration Register
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Page 563 and 564:
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UHCI Controllers Registers16 UHCI C
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UHCI Controllers Registers16.1.4 PC
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UHCI Controllers RegistersBitDescri
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UHCI Controllers Registers16.1.17 U
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UHCI Controllers Registers16.2 USB
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UHCI Controllers RegistersTable 16-
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Page 581 and 582:
Page 583 and 584:
EHCI Controller Registers (D29:F7)1
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EHCI Controller Registers (D29:F7)B
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Page 593 and 594:
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Page 597 and 598:
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EHCI Controller Registers (D29:F7)T
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Page 603 and 604:
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Page 607 and 608:
EHCI Controller Registers (D29:F7)T
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Page 611 and 612:
Page 613 and 614:
PCI-to-PCI Bridge Registers (D30:F0
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Page 617 and 618:
Page 619 and 620:
Page 621 and 622:
Page 623 and 624:
Page 625 and 626:
Page 627 and 628:
AC’97 Audio Controller Registers
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Page 649 and 650:
AC’97 Modem Controller Registers
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Page 663 and 664:
Page 665 and 666:
LPC Interface Bridge Registers (D31
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IDE Controller Registers (D31:F1)22
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Page 741 and 742:
Page 743 and 744:
Page 745 and 746:
IDE Controller Registers (D31:F1)Bi
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SATA Controller Registers (D31:F2)2
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SATA Controller Registers (D31:F2)B
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SATA Controller Registers (D31:F2)T
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SMBus Controller Registers (D31:F3)
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Page 799 and 800:
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Page 803 and 804:
LAN Controller and BMC Registers (B
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High-Precision Event Timer Register
Page 899 and 900:
Page 901 and 902:
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