Intel Pentium III Processor for the SC242 at 450 MHz to 1.0 GHz

More documents

Recommendations

Info

Electrical Specificationsvoltage regulator is stable. This will prevent the possibility of the processor supply going above thespecified VCC CORE in the event of a failure in the supply for the VID lines. In the case of a DC-to-DC converter, this can be accomplished by using the input voltage to the converter for the VID linepull-ups. A resistor of greater than or equal to 10 kΩ may be used to connect the VID signals to theconverter input.2.7 Processor System Bus Unused PinsAll RESERVED pins must remain unconnected. Connection of these pins to VCC CORE , VCC L2 /VCC 3.3 , VSS, or to any other signal (including each other) can result in component malfunction orincompatibility with future Pentium III processors. See Section 5.5 for a pin listing of the processorand the location of each RESERVED pin.All TESTHI pins must be connected to 2.5 V via 1 kΩ –10 kΩ pull-up resistor.PICCLK must be driven with a valid clock input and the PICD[1:0] lines must be pulled-up to2.5 V even when the APIC will not be used. A separate pull-up resistor must be provided for eachAPIC data line.For reliable operation, always connect unused inputs or bidirectional signals to an appropriatesignal level. Unused AGTL+ inputs should be left as no connects; AGTL+ termination is providedon the processor. Unused active low CMOS inputs should be connected through a resistor to 2.5 V.Unused active high inputs should be connected through a resistor to ground (VSS). Unused outputscan be left unconnected. A resistor must be used when tying bidirectional signals to power orground. When tying any signal to power or ground, a resistor will also allow for system testability.For unused pins, it is suggested that ~10 kΩ resistors be used for pull-ups (except for PICD[1:0]discussed above), and ~1 kΩ resistors be used as pull-downs.2.8 Processor System Bus Signal GroupsIn order to simplify the following discussion, the Pentium III processor system bus signals havebeen combined into groups by buffer type. All Pentium III processor system bus outputs are opendrain and require a high-level source provided externally by the termination or pull-up resistor.However, the Pentium III processor includes on-cartridge (CPUID=067xh) or on-die(CPUID=068xh) termination.AGTL+ input signals have differential input buffers, which use V REF as a reference signal. AGTL+output signals require termination to 1.5 V. In this document, the term “AGTL+ Input” refers to theAGTL+ input group as well as the AGTL+ I/O group when receiving. Similarly, “AGTL+ Output”refers to the AGTL+ output group as well as the AGTL+ I/O group when driving.EMI pins may be connected to baseboard ground and/or to chassis ground through zero ohm (0 Ω)resistors. The 0 Ω resistors should be placed in close proximity to the SC242 connector. The path tochassis ground should be short in length and have a low impedance.The CMOS, Clock, APIC, and TAP inputs can each be driven from ground to 2.5 V. The CMOS,APIC, and TAP outputs are open drain and should be pulled high to 2.5 V. This ensures not onlycorrect operation for current Pentium III processors, but compatibility with future Pentium IIIprocessors as well.The groups and the signals contained within each group are shown in Table 4. Refer to Section 7.0for a description of these signals.20 Datasheet
Electrical SpecificationsTable 4.System Bus Signal GroupsGroup NameSignalsAGTL+ InputAGTL+ OutputBPRI#, BR1#, DEFER#, RESET#, RS[2:0]#, RSP#, TRDY#PRDY#AGTL+ I/OA[35:3]#, ADS#, AERR#, AP[1:0]#, BERR#, BINIT#, BNR#, BP[3:2]#, BPM[1:0]#,BR0# 1 , D[63:0]#, DBSY#, DEP[7:0]#, DRDY#, HIT#, HITM#, LOCK#, REQ[4:0]#, RP#CMOS Input 5 A20M#, FLUSH#, IGNNE#, INIT#, LINT0/INTR, LINT1/NMI, PREQ#, PWRGOOD 2 ,SMI#, SLP# 3 , STPCLK#CMOS Output 5 FERR#, IERR#, THERMTRIP# 4System Bus Clock BCLKAPIC Clock PICCLKAPIC I/O 5PICD[1:0]TAP Input 5 TCK, TDI, TMS, TRST#TAP Output 5 TDOPower/Other 6VCC CORE , VCC L2 /VCC 3.3 , VCC 5 , VID[4:0], VTT, VSS, SLOTOCC#, THERMDP, THERMDN,BSEL[1:0], EMI, TESTHI, ReservedNOTES:1. The BR0# pin is the only BREQ# signal that is bidirectional. The internal BREQ# signals are mapped ontoBR# pins after the agent ID is determined. See Section 7.0 for more information.2. See Section 7.0 for information on the PWRGOOD signal.3. See Section 7.0 for information on the SLP# signal.4. See Section 7.0 for information on the THERMTRIP# signal.5. These signals are specified for 2.5 V operation.6. VCC CORE is the power supply for the processor core.VCC L2 /VCC 3.3 is described in Section 2.3.VID[4:0] is described in Section 2.6.VTT is used to terminate the system bus and generate V REF on the processor substrate.VSS is system ground.TESTHI should be connected to 2.5 V with a 1 kΩ –10 kΩ resistor.VCC 5 is not connected to the Pentium III processor core. This supply is used for the test equipment and tools.SLOTOCC# is described in Section 7.0.BSEL[1:0] is described in Section 2.8.2 and Section 7.0.EMI pins are described in Section 7.0.THERMDP, THERMDN are described in Section 7.0.2.8.1 Asynchronous vs. Synchronous for System Bus SignalsAll AGTL+ signals are synchronous to BCLK. All of the CMOS, Clock, APIC, and TAP signalscan be applied asynchronously to BCLK.All APIC signals are synchronous to PICCLK. All TAP signals are synchronous to TCK.Datasheet 21
Page 1 and 2: Intel ® Pentium ® III Processor f
Page 3 and 4: Contents1.0 Introduction...........
Page 5 and 6: Figures1 Second Level (L2) Cache Im
Page 7 and 8: 18 System Bus AC Specifications (TA
Page 9 and 10: Introduction1.0 IntroductionThe Int
Page 11 and 12: Introduction1.1.2 Processor Naming
Page 13 and 14: Electrical Specifications2.0 Electr
Page 15 and 16: Electrical SpecificationsFor the pr
Page 17 and 18: Electrical Specifications2.2.7 Cloc
Page 19: Electrical SpecificationsTable 3.Vo
Page 23 and 24: Electrical SpecificationsFigure 5.
Page 25 and 26: Electrical SpecificationsTable 7.Ab
Page 27 and 28: Electrical SpecificationsTable 8. V
Page 29 and 30: Electrical SpecificationsTable 8. V
Page 31 and 32: Electrical SpecificationsTable 9.AG
Page 33 and 34: Electrical SpecificationsThe timing
Page 35 and 36: Electrical SpecificationsTable 14.
Page 37 and 38: Electrical SpecificationsTable 18.
Page 39 and 40: Electrical SpecificationsFigure 11.
Page 41 and 42: Signal Quality Specifications3.2 AG
Page 43 and 44: Signal Quality Specifications3.2.4
Page 45 and 46: Signal Quality SpecificationsTable
Page 47 and 48: Signal Quality SpecificationsTable
Page 49 and 50: Thermal Specifications and Design C
Page 55 and 56: S.E.C.C. and S.E.C.C.2 Mechanical S
Page 71 and 72:
Intel ® Pentium ® III Processor f
Page 73 and 74:
Page 75 and 76:
Page 77 and 78:
Page 79 and 80:
Page 81 and 82:
Page 83 and 84:
Page 85 and 86:
Page 87 and 88:
S.E.C.C. and S.E.C.C.2 Mechanical S
Page 89 and 90:
Boxed Processor SpecificationsFigur
Page 91 and 92:
Boxed Processor SpecificationsBaseb
Page 93 and 94:
Intel ® Pentium ® III Processor S
Page 95 and 96:
Page 97 and 98:
Page 99 and 100:
Page 101:
show all

Intel Pentium III Processor for the SC242 at 450 MHz to 1.0 GHz

You also want an ePaper? Increase the reach of your titles

Delete template?

Save as template?