Intel Pentium III Processor for the SC242 at 450 MHz to 1.0 GHz

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Boxed Processor SpecificationsFigure 55. Recommended Baseboard Power Header Placement Relative to Fan PowerConnector and Intel ® Pentium ® III Processor242-Contact Slot ConnectorVFan power connector location(1.56 inches above motherboardWXMotherboard fan power header should bepositioned within 4.75 inches of the fanpower connector (lateral distance).Table 40. Baseboard Fan Power Connector LocationFig. Ref.Labels Dimensions (Inches) Min Typ MaxVWXApproximate perpendicular distance of the fan power connectorfrom the center of the 242-contact slot connectorApproximate parallel distance of the fan power connector fromthe edge of the 242-contact slot connectorLateral distance of the baseboard fan power header locationfrom the fan power connector1.441.454.756.4 Fan Heatsink Thermal SpecificationsThis section describes the cooling requirements of the fan heatsink solution utilized by the boxedprocessor.6.4.1 Intel ® Boxed Processor Cooling RequirementsThe boxed processor will be directly cooled with a fan heatsink. However, meeting the processor'stemperature specification is also a function of the thermal design of the entire system, andultimately the responsibility of the system integrator. Refer to Section 4.0 for processortemperature specifications. The boxed processor fan heatsink is able to keep the processortemperature within the specifications (see Table 25 and Table 26) in chassis that provide goodthermal management. For the boxed processor fan heatsink to operate properly, it is critical that theairflow provided to the fan heatsink is unimpeded. Airspace is required around the fan to ensurethat the airflow through the fan heatsink is not blocked. Blocking the airflow to the fan heatsinkreduces the cooling efficiency and decreases fan life. Figure 53 illustrates an acceptable airspaceclearance for the fan heatsink. It is also recommended that the air temperature entering the fan bekept below 45 °C (see Figure 53 for measurement location). Again, meeting the processor'stemperature specification is the responsibility of the system integrator. Refer to Section 4.0 forprocessor temperature specifications.92 Datasheet
Intel ® Pentium ® III Processor Signal Description7.0 Intel ® Pentium®III Processor Signal DescriptionThis section provides an alphabetical listing of all Pentium III processor signals. The tables at theend of this section summarize the signals by direction: output, input, and I/O.7.1 Alphabetical Signals ReferenceTable 41. Signal Description (Sheet 1 of 7)Name Type DescriptionA[35:3]#A20M#ADS#AERR#AP[1:0]#BCLKI/OII/OI/OI/OIThe A[35:3]# (Address) signals define a 2 36 -byte physical memory address space.When ADS# is active, these pins transmit the address of a transaction; when ADS#is inactive, these pins transmit transaction type information. These signals mustconnect the appropriate pins of all agents on the processor system bus. TheA[35:24]# signals are parity-protected by the AP1# parity signal, and the A[23:3]#signals are parity-protected by the AP0# parity signal.On the active-to-inactive transition of RESET#, the processors sample the A[35:3]#pins to determine their power-on configuration. See the Intel ® Pentium ® IIProcessor Developer’s Manual (Document Number 243502) for details.If the A20M# (Address-20 Mask) input signal is asserted, the processor masksphysical address bit 20 (A20#) before looking up a line in any internal cache andbefore driving a read/write transaction on the bus. Asserting A20M# emulates the8086 processor's address wrap-around at the 1-Mbyte boundary. Assertion ofA20M# is only supported in real mode.A20M# is an asynchronous signal. However, to ensure recognition of this signalfollowing an I/O write instruction, it must be valid along with the TRDY# assertion ofthe corresponding I/O Write bus transaction.The ADS# (Address Strobe) signal is asserted to indicate the validity of thetransaction address on the A[35:3]# pins. All bus agents observe the ADS#activation to begin parity checking, protocol checking, address decode, internalsnoop, or deferred reply ID match operations associated with the new transaction.This signal must connect the appropriate pins on all processor system bus agents.The AERR# (Address Parity Error) signal is observed and driven by all processorsystem bus agents, and if used, must connect the appropriate pins on all processorsystem bus agents. AERR# observation is optionally enabled during power-onconfiguration; if enabled, a valid assertion of AERR# aborts the current transaction.If AERR# observation is disabled during power-on configuration, a central agentmay handle an assertion of AERR# as appropriate to the error handling architectureof the system.The AP[1:0]# (Address Parity) signals are driven by the request initiator along withADS#, A[35:3]#, REQ[4:0]#, and RP#. AP1# covers A[35:24]#, and AP0# coversA[23:3]#. A correct parity signal is high if an even number of covered signals arelow and low if an odd number of covered signals are low. This allows parity to behigh when all the covered signals are high. AP[1:0]# should connect the appropriatepins of all processor system bus agents.The BCLK (Bus Clock) signal determines the bus frequency. All processor systembus agents must receive this signal to drive their outputs and latch their inputs onthe BCLK rising edge.All external timing parameters are specified with respect to the BCLK signal.Datasheet 93
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Intel Pentium III Processor for the SC242 at 450 MHz to 1.0 GHz

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