Intel Pentium III Processor for the SC242 at 450 MHz to 1.0 GHz

Signal Quality SpecificationsFigure 16. Low to High AGTL+ and Non-AGTL+ Receiver Ringback ToleranceτV REF+ 0.2αV REFρφV REF- 0.2δ0.7V Clk RefV startClockTimeNote: High to low case is analogousFigure 17. Signal Overshoot/Undershoot, Settling Limit, and RingbackOvershootSettling LimitV HIRising-EdgeRingbackFalling-EdgeRingbackSettling LimitV LOV SSTimeUndershoot3.3.1 Settling Limit GuidelineSettling limit defines the maximum amount of ringing at the receiving pin that a signal must reachbefore its next transition. The amount allowed is 10 percent of the total signal swing (V HI – V LO )above and below its final value. A signal should be within the settling limits of its final value, wheneither in its high state or low state, before it transitions again.Signals that are not within their settling limit before transitioning are at risk of unwantedoscillations which could jeopardize signal integrity. Simulations to verify settling limit may bedone either with or without the input protection diodes present. Violation of the settling limitguideline is acceptable if simulations of 5 to 10 successive transitions do not show the amplitude ofthe ringing increasing in the subsequent transitions.00076748 Datasheet