Intel Pentium III Processor for the SC242 at 450 MHz to 1.0 GHz

Intel ® Pentium ® III Processor Signal DescriptionTable 41. Signal Description (Sheet 6 of 7)Name Type DescriptionRESET#RP#RS[2:0]#RSP#SLOTOCC#II/OIIOAsserting the RESET# signal resets all processors to known states and invalidatestheir L1 and L2 caches without writing back any of their contents. For a Power-on or“warm” reset, RESET# must stay active for at least one millisecond after Vcc COREand CLK have reached their proper specifications. On observing active RESET#,all processor system bus agents will deassert their outputs within two clocks.A number of bus signals are sampled at the active-to-inactive transition of RESET#for power-on configuration. These configuration options are described in the P6Family of Processors Hardware Developer’s Manual (Document Number 244001)for details.The processor may have its outputs tristated via power-on configuration. Otherwise,if INIT# is sampled active during the active-to-inactive transition of RESET#, theprocessor will execute its Built-in Self-Test (BIST). Whether or not BIST isexecuted, the processor will begin program execution at the power on Reset vector(default 0_FFFF_FFF0h). RESET# must connect the appropriate pins of allprocessor system bus agents.The RP# (Request Parity) signal is driven by the request initiator, and providesparity protection on ADS# and REQ[4:0]#. It must connect the appropriate pins ofall processor system bus agents.A correct parity signal is high if an even number of covered signals are low and lowif an odd number of covered signals are low. This definition allows parity to be highwhen all covered signals are high.The RS[2:0]# (Response Status) signals are driven by the response agent (theagent responsible for completion of the current transaction), and must connect theappropriate pins of all processor system bus agents.The RSP# (Response Parity) signal is driven by the response agent (the agentresponsible for completion of the current transaction) during assertion of RS[2:0]#,the signals for which RSP# provides parity protection. It must connect theappropriate pins of all processor system bus agents.A correct parity signal is high if an even number of covered signals are low and lowif an odd number of covered signals are low. While RS[2:0]# = 000, RSP# is alsohigh, since this indicates it is not being driven by any agent guaranteeing correctparity.The SLOTOCC# signal is defined to allow a system design to detect the presenceof a terminator card or processor in a SC242 connector. Combined with the VIDcombination of VID[4:0]= 11111 (see Section 2.6), a system can determine if aSC242 connector is occupied, and whether a processor core is present. See thetable below for states and values for determining the type of cartridge in the SC242connector.SC242 Occupation Truth TableSignal Value StatusSLOTOCC#VID[4:0]0Anything otherthan ‘11111’Processor with core in SC242 connector.SLOTOCC#VID[4:0]SLOTOCC#VID[4:0]0111111Any valueTerminator cartridge in SC242 connector(i.e., no core present).SC242 connector not occupied.SLP#IThe SLP# (Sleep) signal, when asserted in Stop-Grant state, causes processors toenter the Sleep state. During Sleep state, the processor stops providing internalclock signals to all units, leaving only the Phase-Locked Loop (PLL) still operating.Processors in this state will not recognize snoops or interrupts. The processor willrecognize only assertions of the SLP#, STPCLK#, and RESET# signals while inSleep state. If SLP# is deasserted, the processor exits Sleep state and returns toStop-Grant state, restarting its internal clock signals to the bus and APIC processorcore units.98 Datasheet